Datasheet

40
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
10. Power Management and Sleep Modes
10.1 Overview
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving-
power. The AVR provides various sleep modes allowing the user to tailor the power
consumption to the application’s requirements.
10.2 Sleep Modes
Figure 9-1 on page 30 presents the different clock systems in the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P, and their distribu-
tion. The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different
sleep modes and their wake up sources and BOD disable ability
(1)
.
Note: 1. BOD disable is only available for ATmega169PA/329PA/3290PA/6490P.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If either LCD controller or Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which
sleep mode will be activated by the SLEEP instruction. See Table 10-2 on page 45 for a
summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
10.3 BOD Disable
(1)
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses - see Table 28-4 on page
312 and onwards, the BOD is actively monitoring the power supply voltage during a sleep
period. To save power, it is possible to disable the BOD by software for some of the sleep-
modes, see Table 10-1 on page 40. The sleep mode power consumption will then be at the
Table 10-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Sleep Mode
Active Clock Domains Oscillators Wake-up Sources
Software BOD Disable clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main Clock Source Enabled Timer Osc Enabled INT0 and Pin Change USI Start Condition LCD Controller Timer2 SPM/ EEPROM Ready ADC Other I/O
Idle XXXXX
(2)
XXXXXXX
ADC NRM X X X X
(2)
X
(3)
XX
(2)
X
(2)
XX
Power-down X
(3)
XX
Power-save X X X
(3)
XXX X
Standby
(1)
XX
(3)
XX