Datasheet

37
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
9.9 Timer/Counter Oscillator
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P uses the same
crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See ”Low-frequency
Crystal Oscillator” on page 34 for details on the oscillator and crystal requirements.
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P share the
Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the
Timer/Counter Oscillator, the system clock needs to be four times the oscillator frequency. Due
to this and the pin sharing, the Timer/Counter Oscillator can only be used when the Calibrated
Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See ”Asynchronous Operation of Timer/Counter2” on page 158 for further
description on selecting external clock as input instead of a 32.768kHz watch crystal.
9.10 System Clock Prescaler
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P system clock
can be divided by setting the Clock Prescale Register – CLKPR. This feature can be used to
decrease power consumption when the requirement for processing power is low. This can be
used with all clock source options, and it will affect the clock frequency of the CPU and all syn-
chronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in
Table 9-14 on page 39.
9.10.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.