Datasheet

327
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 28-7 on
page 313. The memory page is loaded one byte at a time by supplying the 6 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for a given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 8MSB of the address. If polling is not used,
the user must wait at least t
WD_FLASH
before issuing the next page. (See Table 28-15.)
Accessing the serial programming interface before the Flash write operation completes
can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY
) is not used, the
user must wait at least t
WD_EEPROM
before issuing the next byte (See Table 28-15.) In a
chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 4MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY
) is
not used, the used must wait at least t
WD_EEPROM
before issuing the next page (See Table
28-15). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the con-
tent at the selected address at serial output MISO.
7. At the end of the programming session, RESET
can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET
to “1”.
Tur n V
CC
power off.
Table 28-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
t
WD_FUSE
4.5ms
t
WD_FLASH
4.5ms
t
WD_EEPROM
3.6ms
t
WD_ERASE
9.0ms