Datasheet
307
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 27-2
Note: 1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page 295 and ”RWW – Read-While-
Write Section” on page 295.
Note: 1. Z0: should be zero for all SPM commands, byte select for the LPM instruction. See ”Addressing the Flash During Self-Pro-
gramming” on page 299 for details about the use of Z-pointer during Self-Programming.
27.9 Register Description
27.9.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
Table 27-10. Read-While-Write Limit (ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P)
(1)
Section Pages Address
Read-While-Write section (RWW) 224 0x0000 - 0x37FF
No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF
Table 27-11. Explanation of different variables used in Figure 27-3 on page 300 and the mapping to the Z-pointer
(ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P)
(1)
Variable
Corresponding
Z-value Description
PCMSB 13
Most significant bit in the Program Counter. (Program Counter is 14 bits
PC[13:0])
PAG EM SB 5
Most significant bit which is used to address the words within one page
(64 words in a page requires six/seven bits PC [5:0]).
ZPCMSB Z14
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the
ZPCMSB equals PCMSB + 1.
ZPAGEMSB Z6
Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the
ZPAGEMSB equals PAGEMSB + 1.
PCPAGE PC[13:6] Z14:Z7
Program Counter page address: Page select, for Page Erase and Page
Write
PCWORD PC[5:0] Z6:Z1
Program Counter word address: Word select, for filling temporary buffer
(must be zero during Page Write operation)
Bit 7 6 5 4 3 2 1 0
0x37 (0x57)
SPMIE RWWSB
–
RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0