Datasheet

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

8.4 I/O Memory

The I/O space definition of the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is shown in ”Reg-

ister Summary” on page 679.

All ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P I/Os and

peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD

and ST/STS/STD instructions, transferring data between the 32 general purpose working regis-

ters and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-

accessible using the SBI and CBI instructions. In these registers, the value of single bits can be

checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more

details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F

must be used. When addressing I/O Registers as data space using LD and ST instructions,

0x20 must be added to these addresses.

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a complex

microcontroller with more peripheral units than can be supported within the 64 location reserved

in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most

other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore

be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-

isters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

8.5 General Purpose I/O Registers

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains

three General Purpose I/O Registers. These registers can be used for storing any information,

and they are particularly useful for storing global variables and Status Flags. General Purpose

I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI,

CBI, SBIS, and SBIC instructions.