Datasheet

251
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
• Bit 3 – Reserved
This bit is reserved and will always read as zero.
• Bits 2:0 – LCDCD[2:0]: LCD Clock Divide 2, 1, and 0
The LCDCD[2:0] bits determine division ratio in the clock divider. The various selections are
shown in Table 24-5 on page 251. This Clock Divider gives extra flexibility in frame rate
selection.
The frame frequency can be calculated by the following equation:
Where:
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see Table 24-5 on page 251)
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
101clk
LCD
/1024 520kHz
110clk
LCD
/2048 1MHz
111clk
LCD
/4096 2MHz
Table 24-5. LCD Clock Divide
LCDCD2 LCDCD1 LCDCD0
Output from
Prescaler
divided by (D):
clk
LCD
= 32.768kHz, N = 16, and Duty =
1/4, gives a frame rate of:
000 1 256Hz
001 2 128Hz
010 3 85.3Hz
011 4 64Hz
100 5 51.2Hz
101 6 42.7Hz
110 7 36.6Hz
111 8 32Hz
Table 24-4. LCD Prescaler Select (Continued)
LCDPS2 LCDPS1 LCDPS0
Output from
Prescaler
clk
LCD
/N
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
Frame Rate = 64Hz
f
frame
f
clk
LCD
KND⋅⋅()
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