Datasheet

250
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
Note: 1. LCDPM3 is reserved and will always read as zero in ATmega329A/329PA/649A/649P.
24.5.3 LCDFRR – LCD Frame Rate Register
• Bit 7 – Reserved Bit
This bit is reserved and will always read as zero.
• Bits 6:4 – LCDPS[2:0]: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD[2:0]). The different selections are shown in Table
24-4 on page 250. Together they determine the prescaled LCD clock (clk
LCD_PS
), which is clock-
ing the LCD module.
0 0 1 1 SEG0:18 19
0 1 0 0 SEG0:20 21
0 1 0 1 SEG0:22 23
0 1 1 0 SEG0:23 24
0 1 1 1 SEG0:24 25
1 0 0 0 SEG0:26 27
1 0 0 1 SEG0:28 29
1 0 1 0 SEG0:30 31
1 0 1 1 SEG0:32 33
1 1 0 0 SEG0:34 35
1 1 0 1 SEG0:36 37
1 1 1 0 SEG0:38 39
1 1 1 1 SEG0:39 40
Table 24-3. LCD Port Mask (Values in bold are only available in
ATmega3290A/3290PA/6490A/6490P) (Continued)
LCDPM3 LCDPM2 LCDPM1 LCDPM0
I/O Port in Use as
Segment Driver
Maximum Number
of Segments
Bit 76543210
(0xE6)
–
LCDPS2 LCDPS1 LCDPS0
–
LCDCD2 LCDCD1 LCDCD0 LCDFRR
Read/Write R R/W R/W R/W R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 24-4. LCD Prescaler Select
LCDPS2 LCDPS1 LCDPS0
Output from
Prescaler
clk
LCD
/N
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
Frame Rate = 64Hz
000clk
LCD
/16 8.1kHz
001clk
LCD
/64 33kHz
010clk
LCD
/128 66kHz
011clk
LCD
/256 130kHz
100clk
LCD
/512 260kHz