Datasheet

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

Figure 8-3. On-chip Data SRAM Access Cycles

8.3 EEPROM Data Memory

The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains

512/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which

single bytes can be read and written. The EEPROM has an endurance of at least 100,000

write/erase cycles. The access between the EEPROM and the CPU is described in the follow-

ing, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM

Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

Table 28-9 on page 315, ”Programming via the JTAG Interface” on page 331, and ”Parallel Pro-

gramming Parameters, Pin Mapping, and Commands” on page 314 respectively.

8.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 8-1 on page 23. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code con-

tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered

power supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for

some period of time to run at a voltage lower than specified as minimum for the clock frequency

used. See ”Preventing EEPROM Corruption” on page 25 for details on how to avoid problems in

these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

The following procedure should be followed when writing the EEPROM (the order of steps 3 and

4 is not essential). See ”Register Description” on page 27 for supplementary description for each

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction