Datasheet

219
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
When this bit is wr itten logic one, the digital inp ut buffer on th e AIN1/0 p in is disa bled. The corr espondin g PIN Regi ster bit wil l always read as zero when this bit i s set. When an analog sign al is applied to the AIN1/0 pi n and the digi tal input from t his pin is not needed, this bit should be written lo gic one t o reduce pow er consump tion in the digital input buffer.
23. Analog to Digital Converter
23.1 Features
10-bit Resolution
0.5LSB Integral Non-linearity
± 2LSB Absolute Accuracy
13µs - 260µs Conversion Time (50kHz to 1MHz ADC clock)
Up to 15kSPS at Maximum Resolution (200kHz ADC clock)
Eight Multiplexed Single Ended Input Channels
Optional Left Adjustment for ADC Result Readout
0 - V
CC
ADC Input Voltage Range
Selectable 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
ADC Start Conversion by Auto Triggering on Interrupt Sources
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
23.2 Overview
The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features a
10-bit successive approximation ADC. The ADC is connected to an 8-channel Analog Multi-
plexer which allows eight single-ended voltage inputs constructed from the pins of Port F. The
single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 23-1
on page 220.
The ADC has a separate analog supply voltage pin, AVCC. AV
CC
must not differ more than
± 0.3V from V
CC
. See the paragraph ”ADC Noise Canceler” on page 226 on how to connect this
pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.
The PRADC, in ”PRR – Power Reduction Register” on page 46 must be written to zero to enable
the ADC module.