Datasheet

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

8.2 SRAM Data Memory

Figure 8-2 shows how the SRAM Memory is organized.

The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P is a complex

microcontroller with more peripheral units than can be supported within the 64 locations

reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -

0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower 1280 (ATmega169A/169PA) and 2304/4352

(ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P) data memory locations

address both the Register File, the I/O memory, Extended I/O memory, and the internal data

SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O

memory, then 160 locations of Extended I/O memory, and the next 1024/2048/4096 locations

address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and

the 1,024/2,048 bytes of internal data SRAM in the

ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P are all accessible

through all these addressing modes. The Register File is described in ”General Purpose Regis-

ter File” on page 15.

Figure 8-2. Data Memory Map

8.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 8-3.

32 Registers

64 I/O Registers

Internal SRAM

(1024 X 8)

(2048 x 8)

(4096 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF/0x08FF/0x10FF

0x0060 - 0x00FF

Data Memory

X 8

160 Ext I/O Reg.

0x0100