Datasheet

20
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
8. AVR Memories
This section describes the different memories in the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. The AVR archi-
tecture has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P fea-
tures an EEPROM Memory for data storage. All three memory spaces are linear.
8.1 In-System Reprogrammable Flash Program Memory
The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P contains
16/32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since
all AVR instructions are 16 or 32 bits wide, the Flash is organized as 8K x 16
(ATmega169A/169PA) and 16/32K x 16
(ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA/ATmega649A/ATmega649P/A
Tmega6490A/ATmega6490P). For software security, the Flash Program memory space is
divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles.
The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Program
Counter (PC) is 13/14/15 bits wide, thus addressing the 8/16/32K program memory locations.
The operation of Boot Program section and associated Boot Lock bits for software protection are
described in detail in ”Boot Loader Support – Read-While-Write Self-Programming” on page
294. ”Memory Programming” on page 310 contains a detailed description on Flash data serial
downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-
ing” on page 17.
Figure 8-1. Program Memory Map
0x0000
0x1FFF/0x3FFF/0x7FFF
Program Memory
Application Flash Section
Boot Flash Section