Datasheet

166
8284D–AVR–6/11
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P
19. SPI – Serial Peripheral Interface
19.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
19.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P and peripheral
devices or between several AVR devices. A simplified block diagram of the Serial Peripheral
Interface is shown in Figure 19-1 on page 167.
The PRSPI bit in ”PRR – Power Reduction Register” on page 46 must be written to zero to
enable the SPI module.