Features • • • • • • • • • • • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at16MHz (ATmega169A/169PA/649A/649P) – Up to 20 MIPS Throughput at 20MHz (ATmega329A/329PA/3290A/3290PA/6490A/6490P) – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – In-System Self-programmable Flash P
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Pin Configurations Pinout - 64A (TQFP) and 64M1 (QFN/MLF) LCDCAP 1 (RXD/PCINT0) PE0 2 GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega169A/ATmega169PA/ATmega329A/ATmega329PA/ATmega649A/ATmega649P AVCC Figure 1-1. 64 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1.2 Pinout - 100A (TQFP) Figure 1-2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Pinout - 64MC (DRQFN) Pinout ATmega169A/ATmega169PA A22 B4 B19 A21 A5 B5 B18 B6 A20 B17 A6 A7 A19 B7 B16 A18 Table 1-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2. Overview The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P is a low-power CMOS 8-bit microcontroller based on the Atmel®AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2.2 Comparison Between ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P Table 2-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Port D also serves the functions of various special features of the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P as listed on page 79. 2.3.7 Port E (PE7...PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290PA/6490P as listed on page 90. 2.3.12 RESET Reset input.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.5.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.6.1 SPH and SPL – Stack pointer High and Stack Pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15(1) SP14(1) SP13(1) SP12(1) SP11(1) SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value Note: 7.7 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8. AVR Memories This section describes the different memories in the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features an EEPROM Memory for data storage. All three memory spaces are linear. 8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.2 SRAM Data Memory Figure 8-2 shows how the SRAM Memory is organized. The ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.3 Next Instruction EEPROM Data Memory The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P contains 512/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Wait until EEWE becomes zero. 2. Wait until SPMEN in SPMCSR becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6 8.6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6.3 EEDR – EEPROM Data Register Bit 7 6 5 4 3 2 1 0 0x20 (0x40) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 EEDR • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8.6.6 GPIOR1 – General Purpose I/O Register 1 Bit 8.6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 40. The clock systems are detailed below. Figure 9-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode. 9.1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.4 Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on page 37 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-5. For ceramic resonators, the capacitor values given by the manufacturer should be used. Figure 9-2. Crystal Oscillator Connections C2 C1 XTAL2 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3...
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 9-6. CKSEL0 1 1 1 Notes: 9.6 Start-up Times for the Crystal Oscillator Clock Selection (Continued) SUT1..0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) 01 16K CK 14CK Crystal Oscillator, BOD enabled 10 16K CK 14CK + 4.1ms Crystal Oscillator, fast rising power 11 16K CK 14CK + 65ms Crystal Oscillator, slowly rising power Recommended Usage 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The Low-frequency Crystal Oscillator provides an internal load capacitance, seeTable 9-9 at each TOSC pin. Table 9-9. Capacitance for Low-frequency Oscillator. Device 32kHz Osc. Type Cap(Xtal1/Tosc1) Cap(Xtal2/Tosc2) ATmega169A/169PA/329A/329PA/3290A /3290PA/649A/649P/6490A/6490P System Osc. 16pF 6pF Timer Osc.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 9-3. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-13. Table 9-12. Crystal Oscillator Clock Frequency CKSEL3:0 Frequency Range ATmega169A/169PA/649A/649P 0000 0 - 16MHz ATmega329A/329PA/3290A/3290PA/6490A/6490P 0000 0 - 20MHz Table 9-13. Start-up Times for the External Clock Selection SUT1..
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.9 Timer/Counter Oscillator ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See ”Low-frequency Crystal Oscillator” on page 34 for details on the oscillator and crystal requirements. ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.11 9.11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10. Power Management and Sleep Modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 10.2 Sleep Modes Figure 9-1 on page 30 presents the different clock systems in the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P, and their distribution.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the VCC level has dropped during the sleep period.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 61 for details.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.10 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.10.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 10.11 Register Description 10.11.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. Table 10-2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 10.11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-2. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 11-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 353) will generate a reset, even if the clock is not running.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.2.3 Brown-out Detection ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.3 Internal Voltage Reference ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 11-7. Watchdog Timer WATCHDOG OSCILLATOR 11.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 11.4.2 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 11.5 11.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 12. Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 18. 12.2 Interrupt Vectors Table 12-1. Reset and Interrupt Vectors Vector No.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3290A/3290PA/6490A/6490P Table 12-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x0036 sei 0x0037 xxx ... ... ...
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 12.2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 12.3 12.3.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the picoPower devices ATmega169PA/329PA/3290PA/649P/6490P.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins(2). Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 13-1. Figure 13-1. Pin Change Interrupt pin_lat PCINT(0) D pcint_in_(0) Q 0 pcint_setflag pcint_syn PCIF pin_sync LE x clk PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 13.3 13.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 13-1. 13.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. 13.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13.3.4 PCMSK3 – Pin Change Mask Register 3(1) Bit 7 6 5 4 3 2 1 0 (0x73) – PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK3 • Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30...24 Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Functions” on page 72. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 14-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 14-5 shows how the port pin control signals from the simplified Figure 14-2 on page 67 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 14-5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-2. Signal Name Generic Description of Overriding Signals for Alternate Functions Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.1 Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 14-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-5. 14.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. Table 14-7 and Table 14-8 relate the alternate functions of Port B to the overriding signals shown in Figure 14-5 on page 72.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.3 Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 14-9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-11. Overriding Signals for Alternate Functions in PC3:PC0 14.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-13 and Table 14-14 relates the alternate functions of Port D to the overriding signals shown in Figure 14-5 on page 72. Table 14-13.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 14-15. Table 14-15.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-17.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-20. Overriding Signals for Alternate Functions in PF3:PF0 14.3.7 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 14-21.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 14-21 and Table 14-22 relates the alternate functions of Port G to the overriding signals shown in Figure 14-5 on page 72. Table 14-22.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-23.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • PCINT22/SEG – Port H, Bit 6 PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as an external interrupt source. SEG, LCD front plane 37. • PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as an external interrupt source. SEG, LCD front plane 38. • PCINT20/SEG – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. SEG, LCD front plane 39.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-25 and Table 14-26 relates the alternate functions of Port H to the overriding signals shown in Figure 14-5 on page 72. Table 14-25.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.3.9 Alternate Functions of Port J Port J is only present in ATmega3290A/3290PA/6490A/6490P. The alternate pin configuration is as follows: Table 14-27.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. SEG, LCD front plane 30. • PCINT26/SEG – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source. SEG, LCD front plane 31.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 14-28 on page 92 and Table 14-29 on page 92 relates the alternate functions of Port J to the overriding signals shown in Figure 14-5 on page 72. Table 14-28.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4 14.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.8 PORTC – Port C Data Register Bit 14.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 14.4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 14.4.17 PORTF – Port F Data Register Bit 14.4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 14.4.24 DDRH – Port H Data Direction Register(1) Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xD9) 14.4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output Compare Unit” on page 100. for details. The compare match event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 15.2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled). 15.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 18-4 on page 162). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 15.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) OCRnx - 1 TCNTn OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 15-11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 15-2 and ”Modes of Operation” on page 102. Note: 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on page 104 for more details. Table 15-5 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Compare Output Mode, Phase Correct PWM Mode(1) Table 15-5. COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 15.9.3 OCR0A – Output Compare Register A Bit 7 6 5 0x27 (0x47) 4 3 2 1 0 OCR0A[7:0] OCR0A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 15.9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16. 16-bit Timer/Counter1 16.1 Features • • • • • • • • • • • 16.2 True 16-bit Design (i.e.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 16.2.1 TCCRnB 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion “16.7” on page 121. for more details. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 115. 16.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 133. For fast PWM mode refer to Table 16-3 on page 134, and for phase correct and phase and frequency correct PWM refer to Table 16-4 on page 134. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ( TOP + 1 ) R PCPWM = log ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 16-3 on page 134).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 16.11 Register Description 16.11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 16-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Waveform Generation Mode Bit Description(1) Table 16-5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 17.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4 17.4.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 17-2. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on compare match 1 0 Clear OC0A on compare match 1 1 Set OC0A on compare match Table 17-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 17-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 17-5. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – – OCIE0A TOIE0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 17.4.6 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • • • • • • • 18.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 18-2 shows a block diagram of the counter and its surrounding environment. Figure 18-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page 152). Figure 18-3 shows a block diagram of the Output Compare unit. Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P tion Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A[1:0] bit settings are reserved for certain modes of operation. See ”Register Description” on page 161. 18.6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The timing diagram for the CTC mode is shown in Figure 18-5. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 18-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 18-6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2A to toggle its logical level on each compare match (COM2A[1:0] = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 18.7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A[1:0] to three (See Table 18-5 on page 162). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 18-9 shows the same timing data, but with the prescaler enabled. Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-10 shows the setting of OCF2A in all modes except CTC mode. Figure 18-10.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2A, TCNT2, or OCR2A. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.9.1 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 PSR2 clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.10 Register Description 18.10.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P When OC2A is connected to the pin, the function of the COM2A[1:0] bits depends on the WGM2[1:0] bit setting. Table 18-3 shows the COM2A1:0 bit functionality when the WGM2[1:0] bits are set to a normal or CTC mode (non-PWM). Table 18-3. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 18-6. 18.10.2 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – – OCF2A TOV2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • 19.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 19-1. SPI Block Diagram(1) SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128 Note: 1. Refer to ”Pin Configurations” on page 2, and Table 14-6 on page 75 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2 on page 168. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 19-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19.3 19.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 19.5 19.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 19-5. 19.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P program memory and EEPROM downloading or uploading. See Figure 28-9 on page 324 for serial programming and verification. 19.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20. USART0 20.1 Features • • • • • • • • • • • • 20.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-2. .Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: 20.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 20-3. Synchronous Mode XCK Timing.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 20.7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 20-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 20-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRRn settings in Table 20-3 on page 193. UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz Baud Rate (bps) U2Xn = 0 U2Xn = 1 U2Xn = 0 fosc = 14.7456MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 20-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz Baud Rate (bps) U2Xn = 0 fosc = 18.4320MHz U2Xn = 1 U2Xn = 0 fosc = 20.0000MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 20.11 Register Description 20.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXBn[7:0] UDRn (Read) TXBn[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Figure 20-9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 20-12. UCPOLn Bit Settings Transmitted Data Changed (Output of TxD Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge UCPOLn 20.11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 21. USI – Universal Serial Interface 21.1 Features • • • • • • 21.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 21-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 21-3 on page 206 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P sbrs r16, USIOIF rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 21.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 21.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 21-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 21-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 21-5 on page 210), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 21.3.5 Start Condition Detector The start condition detector is shown in Figure 21-6 on page 210 The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 21.5 21.5.1 Register Description USIDR – USI Data Register Bit 7 6 5 4 3 2 1 0 (0xBA) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Register is accessed directly.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. • Bit 4 – USIDC: Data Output Collision This bit is logical one when bit 7 in the Shift Register differs from the physical pin value.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 21-1. Relations between USIWM1:0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 21-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 21-2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 22. Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 22-1. 22.3 22.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 23. Analog to Digital Converter 23.1 Features • • • • • • • • • • • • • 23.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 23-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 23.5 Prescaling and Conversion Timing Figure 23-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P with Auto triggering from a source other than the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 23-1 on page 224. Figure 23-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 23-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion 1 Cycle Number 2 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Prescaler Reset Sample & Hold Prescaler Reset Conversion Complete MUX and REFS Update Figure 23-7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 23.7 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 23-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 23.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 23.7.3 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 23-10.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 23-11.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 23-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 23-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 23-2. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 510 0x1FE 510 VADCm + /512 VREF Corresponding Decimal Value ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 23.9 23.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 23-3 on page 232.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 23-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 23.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 23-6. 23.9.3 ADC Prescaler Selections (Continued) ADPS2 ADPS1 ADPS0 Division Factor 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register 23.9.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 7 – Reserved This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written. • Bit 2:0 – ADTS[2:0:] ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 24. LCD Controller 24.1 Features • • • • • • • • • • • • 24.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 24-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P To energize a segment, an absolute voltage above a certain threshold must be applied. This is done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase. For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage levels must be applied. Otherwise, non-energized segments on COM0 would be energized for all non-selected common.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P mum drive time of approximately 2ms when using 1/2 or 1/4 duty, and approximately 2.7ms when using 1/3 duty. To achieve satisfactory contrast, all segments on the LCD display must therefore be able to be fully charged/discharged within 2 or 2.7ms, depending on the number of common pins. 24.2.9 Minimizing power consumption By keeping the percentage of the time the LCD drivers are turned on at a minimum, the power consumption of the LCD driver can be minimized.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 24-4. Driving a LCD with Two Common Terminals VLCD VLCD SEG0 GND 1/ VLCD 2VLCD GND 1/ VLCD 2VLCD -1/ GND V 2 LCD -VLCD COM0 VLCD 1/ V 2 LCD COM1 GND VLCD 1/ V 2 LCD SEG0 - COM0 SEG0 - COM1 GND -1/ V 2 LCD -VLCD Frame 24.3.3 SEG0 GND Frame Frame Frame 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is shown in Figure 24-5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 24-6. Driving a LCD with Four Common Terminals VLCD 2/ 3VLCD 1/ 3VLCD VLCD SEG0 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD VLCD COM0 2/ 3VLCD 1/ 3VLCD GND 3VLCD 1/ 3VLCD GND -1/3VLCD -2/3VLCD -VLCD 24.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P (TOSC1) pin instead of a 32kHz crystal. See ”Asynchronous Operation of Timer/Counter2” on page 158 for further details. Before entering Power-down mode, Standby mode or ADC Noise Reduction mode with synchronous LCD clock selected, the user have to disable the LCD. Refer to ”Disabling the LCD” on page 246. 24.3.7 Display Blanking When LCDBL is written to one, the LCD is blanked after completing the current frame.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 24.4 LCD Usage The following section describes how to use the LCD. 24.4.1 LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization process normally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but can also be adjusted during operation. Consider the following LCD as an example: Figure 24-8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example(1) LCD_Init: ; Use 32 kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 24.4.2 Updating the LCD Display memory (LCDDR0, LCDDR1,...), LCD Blanking (LCDBL), Low power waveform (LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no restrictions on writing these LCD Register locations, but an LCD data update may be split between two frames if data are latched while an update is in progress.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Assembly Code Example(1) LCD_disable: ; Wait until a new frame is started. Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; Set LCD Blanking and clear interrupt flag ; by writing a logical one to the flag. ldi r16, (1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 24.5 24.5.1 Register Description LCDCRA – LCD Control and Status Register A Bit 7 6 5 4 3 2 1 0 LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL Read/Write R/W R/W R R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 (0xE4) LCDCRA • Bit 7 – LCDEN: LCD Enable Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned off immediately.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 0 – LCDBL: LCD Blanking When this bit is written to one, the display will be blanked after completion of a frame. All segment and common pins will be driven to ground. 24.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 24-3. LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O Port in Use as Segment Driver Maximum Number of Segments 0 0 1 1 SEG0:18 19 0 1 0 0 SEG0:20 21 0 1 0 1 SEG0:22 23 0 1 1 0 SEG0:23 24 0 1 1 1 SEG0:24 25 1 0 0 0 SEG0:26 27 1 0 0 1 SEG0:28 29 1 0 1 0 SEG0:30 31 1 0 1 1 SEG0:32 33 1 1 0 0 SEG0:34 35 1 1 0 1 SEG0:36 37 1 1 1 0 SEG0:38 39 1 1 1 1 SEG0:39 40 Note: 24.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 24-4. LCD Prescaler Select (Continued) LCDPS2 LCDPS1 LCDPS0 Output from Prescaler clkLCD/N Applied Prescaled LCD Clock Frequency when LCDCD2:0 = 0, Duty = 1/4, and Frame Rate = 64Hz 1 0 1 clkLCD/1024 520kHz 1 1 0 clkLCD/2048 1MHz 1 1 1 clkLCD/4096 2MHz • Bit 3 – Reserved This bit is reserved and will always read as zero.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation is shown in Table 24-6 on page 252. Table 24-6. 24.5.4 Example of frame rate calculation clkLCD duty K N LCDCD2:0 D Frame Rate 4MHz 1/4 8 2048 011 4 4000000/(8*2048*4) = 61Hz 4MHz 1/3 6 2048 011 4 4000000/(6*2048*4) = 81Hz 32.768kHz Static 8 16 000 1 32768/(8*16*1) = 256Hz 32.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bits 3:0 – LCDCC[3:0]: LCD Contrast Control The LCDCC[3:0] bits determine the maximum voltage VLCD on segment and common pins. The different selections are shown in Table 24-8. New values take effect every beginning of a new frame. Table 24-8. LCD Contrast Control LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum Voltage VLCD 0 0 0 0 2.60 0 0 0 1 2.65 0 0 1 0 2.70 0 0 1 1 2.75 0 1 0 0 2.80 0 1 0 1 2.85 0 1 1 0 2.90 0 1 1 1 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 24.5.5 LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visible). Unused LCD Memory bits for the actual display can be used freely as storage.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 25. JTAG Interface and On-chip Debug System 25.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 25-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 259. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26. IEEE 1149.1 (JTAG) Boundary-scan 26.1 Features • • • • • 26.2 JTAG (IEEE std. 1149.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 26.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 26-1. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 26.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 264 for a complete description. 26.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 26.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 26-3 on page 266 to make the scan chain read the actual pin value.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 26-3. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR WDx RESET OCxn DATA BUS RDx Pxn 1 Q ODxn IDxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 26.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.5.3 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 26-5 shows how each Oscillator with external connection is supported in the scan chain.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.5.4 Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 26-6. The Boundary-scan cell from Figure 26-7 is attached to each of these signals. The signals are described in Table 26-3 on page 269. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 26-6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-3. 26.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: The upper limit is: 1024 ⋅ 1.5V ⋅ 0.95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1.5V ⋅ 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.6 ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P Boundary-scan Order Table 26-7 on page 279 and Table 26-8 on page 286 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6. ATmega169A/169PA Boundary-scan Order (Continued) Bit Number Signal Name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6. ATmega169A/169PA Boundary-scan Order (Continued) Bit Number Signal Name Module 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6. ATmega169A/169PA Boundary-scan Order (Continued) Bit Number Signal Name 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.Control 75 PD5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6. ATmega169A/169PA Boundary-scan Order (Continued) Bit Number Signal Name 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pull-up_Enable 41 PC7.Data 40 PC7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-6. ATmega169A/169PA Boundary-scan Order (Continued) Bit Number Signal Name 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pull-up_Enable 5 PF1.Data 4 PF1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7. ATmega329A/329PA/649A/649P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7. ATmega329A/329PA/649A/649P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 133 PB0.Data 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7. ATmega329A/329PA/649A/649P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 100 EXTCLKEN 99 OSCON 98 RCOSCEN 97 OSC32EN 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7. ATmega329A/329PA/649A/649P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 64 PG1.Control 63 PG1.Pull-up_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-7. ATmega329A/329PA/649A/649P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name 135 EXTCLK (XTAL1) 134 OSCCK 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.Control 117 PJ6.Pull-up_Enable 116 PD0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 26-8. ATmega3290A/3290PA/6490A/6490P Boundary-scan Order, 100-pin Bit Number Signal Name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.8 26.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 27. Boot Loader Support – Read-While-Write Self-Programming 27.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 27.2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 27.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 27-1. Read-While-Write vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 27-2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 27-2. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 27.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 27-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: 27.8 1. The different variables used in Figure 27-3 on page 300 are listed in Table 27-11 on page 307. 2. PCPAGE and PCWORD are listed in Table 28-13 on page 324.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 27.8.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P as described in ”Interrupts” on page 56, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example for a Boot Loader” on page 304 for an example. 27.8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 28-4 on page 312 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 27.8.12 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 27-7. Read-While-Write Limit (ATmega169A/169PA)(1) Section Pages Read-While-Write section (RWW) 112 0x0000 - 0x1BFF No Read-While-Write section (NRWW) 16 0x1C00 - 0x1FFF Note: 1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page 295 and ”RWW – Read-While-Write Section” on page 295. Table 27-8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Note: 1. The different BOOTSZ Fuse configurations are shown in Figure 27-2 Table 27-10. Read-While-Write Limit (ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490P)(1) Section Pages Address Read-While-Write section (RWW) 224 0x0000 - 0x37FF No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF Note: 1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page 295 and ”RWW – Read-WhileWrite Section” on page 295.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P • Bit 6 – RWWSB: Read-While-Write Section Busy When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28. Memory Programming 28.1 Program And Data Memory Lock Bits The ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 28-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 28-1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Lock Bit Protection Modes(1)(2) (Continued) Table 28-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 28.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-8. 28.6 No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB 1Kbytes 4 bytes EEA[1:0] 256 EEA[13:2] 13 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-9. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1 (“0” selects low byte, “1” selects high byte). XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-12. Command Byte Bit Coding Command Byte 28.7 28.7.1 Command Executed 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel Programming Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to “0” and toggle XTAL1 at least six times. 3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.7.4 Programming the Flash The Flash is organized in pages, see Table 28-7 on page 313. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 28-3 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 1. “XX” is don’t care. The letters refer to the programming description above.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 28-8 on page 314. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 317 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 317 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 28.7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 28.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 317 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 28.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 317 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 28-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 28-9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-13.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 28-7 on page 313. The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load Program Memory Page instruction.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 28.8.3 Serial Programming Instruction set Table 28-16 and Figure 28-12 on page 330 describes the Instruction set. Table 28-16.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-16.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-12. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB A Bit 15 B Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 28.8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.9 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.9.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.9.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific JTAG Instructions” on page 331. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 28.9.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-15.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-17. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 28-17. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 28-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 28.9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 28-17.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 28.9.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 28-13 on page 324). 28.9.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 341. 1. Enter JTAG instruction PROG_COMMANDS. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 28-7 on page 313) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 28-13 on page 324). 28.9.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29. Electrical Characteristics 29.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 29-1. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.2.1 ATmega169A DC Characteristics Table 29-2. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Condition Power Supply Current(1) ICC (2) Power-save mode Power-down mode(2) Notes: Typ. Max. Active 1MHz, VCC = 2V 0.35 1.0 Active 4MHz, VCC = 3V 2.3 3.5 Active 8MHz, VCC = 5V 8.4 12.0 Idle 1MHz, VCC = 2V 0.1 0.45 Idle 4MHz, VCC = 3V 0.7 1.2 Idle 8MHz, VCC = 5V 3.0 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.2.3 ATmega329A DC Characteristics Table 29-4. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current(1) ICC Power-save mode Power-down mode(1) Notes: Min. Typ. Max. Active 1MHz, VCC = 2V 0.8 1.5 Active 4MHz, VCC = 3V 2.6 3.5 Active 8MHz, VCC = 5V 6.0 12.0 Idle 1MHz, VCC = 2V 0.2 0.45 Idle 4MHz, VCC = 3V 0.7 1.5 Idle 8MHz, VCC = 5V 1.8 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.2.5 ATmega3290A DC Characteristics Table 29-6. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Min. Typ. Max. Active 1MHz, VCC = 2V 0.8 1.5 Active 4MHz, VCC = 3V 2.6 3.5 Active 8MHz, VCC = 5V 6.0 12.0 Idle 1MHz, VCC = 2V 0.2 0.45 Idle 4MHz, VCC = 3V 0.7 1.5 Idle 8MHz, VCC = 5V 1.8 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.2.7 ATmega649A DC Characteristics Table 29-8. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Min. Typ. Max. Active 1MHz, VCC = 2V 1.1 1.5 Active 4MHz, VCC = 3V 2.8 3.5 Active 8MHz, VCC = 5V 7.0 12.0 Idle 1MHz, VCC = 2V 0.3 0.45 Idle 4MHz, VCC = 3V 0.8 1.5 Idle 8MHz, VCC = 5V 2.5 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.2.9 ATmega6490A DC Characteristics Table 29-10. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Power Supply Current ICC Power-save mode Power-down mode Notes: Condition Min. Typ. Max. Active 1MHz, VCC = 2V 1.1 1.5 Active 4MHz, VCC = 3V 2.8 3.5 Active 8MHz, VCC = 5V 7.0 12.0 Idle 1MHz, VCC = 2V 0.3 0.45 Idle 4MHz, VCC = 3V 0.8 1.5 Idle 8MHz, VCC = 5V 2.5 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.3 Speed Grades Maximum frequency is depending on VCC. As shown in Figure 29-1, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7 and between 2.7V < VCC < 4.5. Figure 29-1. Maximum Frequency vs. VCC, ATmega169A/169PA/ATmega649A/ATmega649P 16 MHz 8 MHz Safe Operating Area 4 MHz 1.8V 2.7V 4.5V 5.5V Figure 29-2. Maximum Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.4 29.4.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 29-12. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy 8.0MHz 3V 25°C ±10% 7.3 - 8.1MHz 1.8V - 5.5V(1) -40°C - 85°C ±1% Factory Calibration User Calibration Notes: 29.4.2 1. Voltage range for ATmega169A/169PA/329A/329PA/649A/649P/3290A/3290PA/6490A/6490P. External Clock Drive Waveforms Figure 29-3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.5 System and Reset Characteristics The following characteristics apply only to ATmega169A/169PA Table 29-14. Reset, Brown-out, and Internal Voltage Characteristics Symbol Min Typ Max Power-on Reset Threshold Voltage (rising) TA = -40°C to 85°C 1.1 1.4 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.6.2 ATmega329A/329PA/3290A/3290PA/649A/649P/6490A/6490PA revision A and B Table 29-16. Reset, Brown-out, and Internal Voltage Reference Characteristics, TA = -40°C to 85°C Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) Note: 29.7 Typ Max 0.7 1.0 1.4 0.05 0.9 1.3 Units V (1) Power-on Slope Rate SRON Min. 0.01 4.5 V/ms 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.9 SPI Timing Characteristics See Figure 29-4 on page 355 and Figure 29-5 on page 356 for details. Table 29-19. SPI Timing Parameters Description Mode 1 SCK period Master See Table 19-5 on page 174 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 29-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.10 ADC Characteristics Table 29-20. ADC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table 29-20. ADC Characteristics Symbol Parameter Condition Min. Typ. Max. Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Notes: 1. Voltage difference between channels 29.11 LCD Controller Characteristics Table 29-21. LCD Controller Characteristics Symbol Parameter ILCD LCD Driver Current RSEG RCOM Condition Total for All COM and SEG pins Min.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-2. ATmega169A: Active Supply Current vs. Frequency (1 - 16MHz) 11 10 5.5 V 9 5.0 V 8 4.5 V ICC (mA) 7 6 4.0 V 5 4 3.3 V 3 2.7 V 2 1 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 30-3. ATmega169A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 6 85 °C 25 °C -45 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-4. ATmega169A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 25 °C 85 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-5. ATmega169A: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 85 °C 25 °C -45 °C 35 30 ICC (µA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.2 Idle Supply Current Figure 30-6. ATmega169A: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) 0.25 5.5 V ICC (mA) 0.2 5.0 V 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-7. ATmega169A: Idle Supply Current vs. Frequency (1 - 16MHz) 3.5 5.5 V 3 5.0 V 4.5 V ICC (mA) 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-8. ATmega169A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 25 °C 85 °C 1.75 -45 °C 1.5 ICC (mA) 1.25 1 0.75 0.5 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-9. ATmega169A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.4 85 °C 25 °C -45 °C 0.35 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-10. ATmega169A: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9 85 °C 25 °C -45 °C 8 7 ICC (µA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.3 ATmega169A: Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.3.1 Example 1 Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. From Table 30-2, second column, we see that we need to add 13.1% for the USART0, 13.0% for the SPI, and 13.2% for the TIMER1 module. Reading from Figure 30-6, we find that the idle current consumption is ~0.09 mA at VCC = 3.0V and F = 1MHz.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-12. ATmega169A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.1.5 Power-save Supply Current Figure 30-13. ATmega169A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2 85 °C 1.8 1.6 ICC (µA) 1.4 1.2 25 °C 1 -45 °C 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.6 Standby Supply Current Figure 30-14. ATmega169A Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 85 °C 2 1.8 1.6 ICC (µA) 1.4 1.2 1 25 °C 0.8 -45 °C 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-15. ATmega169A: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.18 6MHz_res 6MHz_xtal 0.16 4MHz_xtal 4MHz_res 0.14 ICC (mA) 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.7 Pin Pull-up Figure 30-16. ATmega169A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 150 125 IOP (uA) 100 75 50 25 °C 85 °C -45 °C 25 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 30-17. ATmega169A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 85 °C 25 °C -45 °C 10 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-18. ATmega169A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 25 °C 85 °C -45 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP (V) Figure 30-19. ATmega169A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-20. ATmega169A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 25 °C 85 °C -45 °C 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 30-21. ATmega169A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 85 °C -45 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.8 Pin Driver Strength Figure 30-22. ATmega169A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH (V) 4.9 4.85 4.8 4.75 -45 °C 4.7 25 °C 4.65 85 °C 4.6 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-23. ATmega169A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH (V) 2.5 2.4 2.3 -45 °C 2.2 25 °C 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-24. ATmega169A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 25 °C 85 °C 1.4 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH (mA) Figure 30-25. ATmega169A: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 4.4 85 °C 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-26. ATmega169A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 85 °C 1.4 1.2 1 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-27. ATmega169A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.9 1.8 VOH (V) 1.7 1.6 1.5 -45 °C 1.4 25 °C 85 °C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-28. ATmega169A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 1.1 85 °C 1 0.9 0.8 25 °C VOL (V) 0.7 0.6 -45 °C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-29. ATmega169A. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.1 85 °C 1 0.9 0.8 25 °C VOL (V) 0.7 0.6 -45 °C 0.5 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-30. ATmega169A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.5 85 °C 0.4 25 °C VOL (V) 0.3 -45 °C 0.2 0.1 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 IOL (mA) VOL (V) Figure 30-31. ATmega169A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 -45 °C 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-32. ATmega169A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-33. ATmega169A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.4 25 °C 0.3 VOL (V) -45 °C 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.9 Pin Threshold and Hysteresis Figure 30-34. ATmega169A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-35. ATmega169A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0” 2.4 85 °C 25 °C -45 °C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-36. ATmega169A: I/O Pin Input Hysteresis vs. VCC 0.65 -45 °C 25 °C 85 °C Input Hysteresis (mV) 0.6 0.55 0.5 0.45 0.4 0.35 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-37. ATmega169A: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 -45 °C 25 °C 85 °C 2.3 Threshold (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-38. ATmega169A: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 85 °C 25 °C -45 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-39. ATmega169A: Reset Input Pin Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.10 BOD Thresholds and Analog Comparator Offset Figure 30-40. ATmega169A: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.37 Rising Vcc BOD threshold (V) 4.35 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.23 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-41. ATmega169A: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc BOD threshold (V) 2.752 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-42. ATmega169A: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.831 Rising Vcc 1.826 BOD threshold (V) 1.821 1.816 1.811 Falling Vcc 1.806 1.801 1.796 1.791 1.786 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-43. ATmega169A: Bandgap Voltage vs. VCC 1.105 1.1 Bandgap Voltage (V) 1.095 85 °C 25 °C 1.09 1.085 1.08 1.075 1.07 -45 °C 1.065 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-44. ATmega169A: Bandgap Voltage vs. Temperature 1.102 1.8 V 2.7 V 4.0 V 5.5 V Bandgap Voltage (V) 1.097 1.092 1.087 1.082 1.077 1.072 1.067 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-45. ATmega169A: Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Comparator Offset Voltage (V) 0.007 85 °C 25 °C 0.006 -40 °C 0.005 0.004 0.003 0.002 0.001 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Comparator Offset Voltage (V) Figure 30-46. ATmega169A: Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) CC 0.003 85 °C 0.0025 25 °C -40 °C 0.002 0.0015 0.001 0.0005 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Common Mode Voltage (V) 30.1.11 Internal Oscillator Speed Figure 30-47. ATmega169A: Watchdog Oscillator Frequency vs. VCC 1300 -45 °C 25 °C 85 °C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-48. ATmega169A: Watchdog Oscillator Frequency vs. Temperature 1300 FRC (kHz) 1250 5.5 V 1200 5.0 V 1150 4.5 V 4.0 V 3.0 V 2.7 V 1100 1.8 V 1050 1000 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Figure 30-49. ATmega169A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.5 V 3.3 V 8.2 8.1 1.8 V FRC (MHz) 8 7.9 7.8 7.7 7.6 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-50. ATmega169A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C FRC (MHz) 8 7.9 7.8 -45 °C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-51. ATmega169A: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.12 Current Consumption of Peripheral Units Figure 30-52. ATmega169A: Brownout Detector Current vs. VCC 44 40 36 ICC (uA) 32 28 85 °C 25 °C -45 °C 24 20 16 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-53. ATmega169A: Active Supply Current with ADC at 50kHz vs. VCC 400 375 85 °C 25 °C -45 °C 350 ICC (uA) 325 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-54. ATmega169A: Active Supply Current , p with ADC at 200kHz vs. VCC 375 85 °C -45 °C 25 °C 350 325 ICC (uA) 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-55. ATmega169A: Active Supply Current with ADC at 1MHz vs. VCC 350 85 °C 25 °C -45 °C 325 300 ICC (uA) 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-56. ATmega169A: AREF External Reference Current vs. VCC 180 85 °C 25 °C -45 °C 160 ICC (uA) 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-57. ATmega169A: Watchdog Timer Current vs. VCC 30 85 °C 25 °C -45 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-58. ATmega169A: Analog Comparator Current vs. VCC 85 -45 °C 80 75 25 °C 85 °C 70 ICC (uA) 65 60 55 50 45 40 35 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-59. ATmega169A: Programming Current vs. VCC 16 14 -45 °C 25 °C 12 85 °C ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.1.13 Current Consumption in Reset and Reset Pulswidth Figure 30-60. ATmega169A: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 5.5 V 0.14 5.0 V 0.12 4.5 V ICC (mA) 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-61. ATmega169A: Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 2.1 5.5 V 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-62. ATmega169A: Minimum Reset Pulse Width vs. VCC 2400 Pulsewidth (ns) 2000 1600 1200 800 85 °C 25 °C -45 °C 400 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.2 30.2.1 ATmega169PA Active Supply Current Figure 30-63. ATmega169PA: Active Supply Current vs. Frequency (0.1 - 1.0MHz) 1.2 5.5 V 1 5.0 V ICC (mA) 0.8 4.5 V 4.0 V 0.6 3.3 V 0.4 2.7 V 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-64. ATmega169PA: Active Supply Current vs. Frequency (1 - 16MHz) 11 10 5.5 V 9 5.0 V 8 4.5 V ICC (mA) 7 6 4.0 V 5 4 3.3 V 3 2.7 V 2 1 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-65. ATmega169PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 6 85 °C 25 °C -45 °C 5 ICC (mA) 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-66. ATmega169PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 25 °C 85 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-67. ATmega169PA: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 85 °C 25 °C -45 °C 35 30 ICC (µA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.2 Idle Supply Current Figure 30-68. ATmega169PA: Idle Supply Current vs. Frequency (0.1 - 1.0MHz) 0.25 5.5 V ICC (mA) 0.2 5.0 V 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 0.05 1.8 V 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-69. ATmega169PA: Idle Supply Current vs. Frequency (1 - 16MHz) 3.5 5.5 V 3 5.0 V 4.5 V ICC (mA) 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 30-70. ATmega169PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 25 °C 85 °C 1.75 -45 °C 1.5 ICC (mA) 1.25 1 0.75 0.5 0.25 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-71. ATmega169PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.4 85 °C 25 °C -45 °C 0.35 0.3 ICC (mA) 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-72. ATmega169PA: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9 85 °C 25 °C -45 °C 8 7 ICC (µA) 6 5 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-3. ATmega169PA: Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz Table 30-4. VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 7µA 44µA 195µA PRUSART0 6.9µA 43.5µA 210µA PRSPI 6.6µA 47µA 205µA PRTIM1 7µA 47µA 206µA PRLCD 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.2.4 Power-down Supply Current Figure 30-73. ATmega169PA: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 1.4 85 °C 1.2 ICC (uA) 1 0.8 0.6 0.4 -45 °C 25 °C 0.2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-74. ATmega169PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.2.5 Power-save Supply Current Figure 30-75. ATmega169PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 2 85 °C 1.8 1.6 ICC (µA) 1.4 1.2 25 °C 1 -45 °C 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. 30.2.6 Standby Supply Current Figure 30-76. ATmega169PA: Standby Supply Current vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-77. ATmega169PA: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled g p p p g p p 0.18 6MHz_res 6MHz_xtal 0.16 4MHz_xtal 4MHz_res 0.14 ICC (mA) 0.12 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.7 Pin Pull-up Figure 30-78. ATmega169PA: I/O Pin Pull-up Resistor Current vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-79. ATmega169PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 85 °C 25 °C -45 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 30-80. ATmega169PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 25 °C 85 °C -45 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-81. ATmega169PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET (uA) 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) Figure 30-82. ATmega169PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=2.7V) 60 50 IRESET (uA) 40 30 20 25 °C 85 °C -45 °C 10 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-83. ATmega169PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C 85 °C -45 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET (V) 30.2.8 Pin Driver Strength Figure 30-84. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH (V) 4.9 4.85 4.8 4.75 -45 °C 4.7 25 °C 4.65 85 °C 4.6 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-85. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH (V) 2.5 2.4 2.3 -45 °C 2.2 25 °C 2.1 85 °C 2 0 2 4 6 8 10 IOH (mA) Figure 30-86. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 25 °C 85 °C 1.4 1.3 1.2 1.1 1 0 0.5 1 1.5 2 2.5 3 3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-87. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 4.4 85 °C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-88. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 85 °C 1.4 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-89. ATmega169PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.9 1.8 VOH (V) 1.7 1.6 1.5 -45 °C 1.4 25 °C 85 °C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (mA) Figure 30-90. ATmega169PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 1.1 85 °C 1 0.9 0.8 25 °C VOL (V) 0.7 0.6 -45 °C 0.5 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-91. ATmega169PA. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.1 85 °C 1 0.9 0.8 25 °C VOL (V) 0.7 0.6 -45 °C 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-92. ATmega169PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.5 85 °C 0.4 25 °C VOL (V) 0.3 -45 °C 0.2 0.1 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P VOL (V) Figure 30-93. ATmega169PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 -45 °C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-94. ATmega169PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-95. ATmega169PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.4 25 °C 0.3 VOL (V) -45 °C 0.2 0.1 0 0 1 2 3 4 5 6 IOL (mA) 30.2.9 Pin Threshold and Hysteresis Figure 30-96. ATmega169PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-97. ATmega169PA. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0” 2.4 85 °C 25 °C -45 °C 2.1 Threshold (V) 1.8 1.5 1.2 0.9 0.6 0.3 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-98. ATmega169PA: I/O Pin Input Hysteresis vs. VCC 0.65 -45 °C 25 °C 85 °C Input Hysteresis (mV) 0.6 0.55 0.5 0.45 0.4 0.35 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-99. ATmega169PA: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 -45 °C 25 °C 85 °C 2.3 Threshold (V) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-100.ATmega169PA: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.4 85 °C 25 °C -45 °C 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-101.ATmega169PA: Reset Input Pin Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.10 BOD Thresholds and Analog Comparator Offset Figure 30-102.ATmega169PA: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.37 Rising Vcc BOD threshold (V) 4.35 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-103.ATmega169PA: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.767 Rising Vcc BOD threshold (V) 2.752 2.737 2.722 2.707 Falling Vcc 2.692 2.677 2.662 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-104.ATmega169PA: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.831 Rising Vcc 1.826 BOD threshold (V) 1.821 1.816 1.811 Falling Vcc 1.806 1.801 1.796 1.791 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-105.ATmega169PA: Bandgap Voltage vs. VCC 1.105 1.1 Bandgap Voltage (V) 1.095 85 °C 25 °C 1.09 1.085 1.08 1.075 1.07 -45 °C 1.065 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 30-106.ATmega169PA: Bandgap Voltage vs. Temperature 1.102 1.8 V 2.7 V 4.0 V 5.5 V Bandgap Voltage (V) 1.097 1.092 1.087 1.082 1.077 1.072 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-107.ATmega169PA: Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Comparator Offset Voltage (V) 0.007 85 °C 25 °C 0.006 -40 °C 0.005 0.004 0.003 0.002 0.001 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 Common Mode Voltage (V) Comparator Offset Voltage (V) Figure 30-108.ATmega169PA: Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 0.003 85 °C 0.0025 25 °C -40 °C 0.002 0.0015 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.2.11 Internal Oscillator Speed Figure 30-109.ATmega169PA: Watchdog Oscillator Frequency vs. VCC 1300 -45 °C 25 °C 85 °C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-110.ATmega169PA: Watchdog Oscillator Frequency vs. Temperature 1300 FRC (kHz) 1250 5.5 V 1200 5.0 V 1150 4.5 V 4.0 V 3.0 V 2.7 V 1100 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-111.ATmega169PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.5 V 3.3 V 8.2 8.1 1.8 V FRC (MHz) 8 7.9 7.8 7.7 7.6 7.5 -50 -30 -10 10 30 50 70 90 Temperature (°C) Figure 30-112.ATmega169PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C FRC (MHz) 8 7.9 7.8 -45 °C 7.7 7.6 7.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-113.ATmega169PA: Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 85 °C 25 °C -45 °C 16 14 FRC (MHz) 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 30.2.12 Current Consumption of Peripheral Units Figure 30-114.ATmega169PA: Brownout Detector Current vs. VCC 44 40 36 ICC (uA) 32 28 85 °C 25 °C -45 °C 24 20 16 12 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-115.ATmega169PA: Active Supply Current with ADC at 50kHz vs. VCC 400 375 85 °C 25 °C -45 °C 350 ICC (uA) 325 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-116.ATmega169PA: Active Supply Current with ADC at 200kHz vs. VCC 85 °C -45 °C 25 °C 350 325 ICC (uA) 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-117.ATmega169PA: Active Supply Current with ADC at 1MHz vs. VCC 350 85 °C 25 °C -45 °C 325 300 ICC (uA) 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-118.ATmega169PA: AREF External Reference Current vs. VCC 180 85 °C 25 °C -45 °C 160 ICC (uA) 140 120 100 80 60 40 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-119.ATmega169PA: Watchdog Timer Current vs. VCC 30 85 °C 25 °C -45 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-120.ATmega169PA: Analog Comparator Current vs. VCC 85 -45 °C 80 75 25 °C 85 °C 70 ICC (uA) 65 60 55 50 45 40 35 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-121.ATmega169PA: Programming Current vs. VCC 16 14 -45 °C 25 °C 12 85 °C ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.2.13 Current Consumption in Reset and Reset Pulswidth Figure 30-122.ATmega169PA: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 5.5 V 0.14 5.0 V 0.12 4.5 V ICC (mA) 0.1 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-123.ATmega169PA: Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 2.1 5.5 V 1.8 5.0 V ICC (mA) 1.5 4.5 V 1.2 4.0 V 0.9 3.3 V 0.6 2.7 V 0.3 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 30-124.ATmega169PA: Minimum Reset Pulse Width vs. VCC 2400 Pulsewidth (ns) 2000 1600 1200 800 85 °C 25 °C -45 °C 400 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3 30.3.1 ATmega329A Active Supply Current Figure 30-125.ATmega329A: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.4 5.5 V 1.2 5.0 V ICC [mA] 1 4.5 V 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 30-126.ATmega329A: Active Supply Current vs. Frequency (1 - 20MHz) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-127.ATmega329A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25°C -40°C 6.5 6 5.5 ICC [mA] 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-128.ATmega329A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 85 °C 1.4 25°C -40°C ICC [mA] 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ICC [mA] Figure 30-129.ATmega329A: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.3.2 Idle Supply Current Figure 30-130.ATmega329A: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) ICC [MHz] 0.35 0.3 5.5 V 0.25 5.0 V 4.5 V 4.0 V 3.3 V 0.2 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-131.ATmega329A: Idle Supply Current vs. Frequency (1 - 20MHz) 5 4.5 5.5 V 4 5.0 V ICC [MHz] 3.5 4.5 V 3 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 30-132.ATmega329A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 1.8 85 °C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-133.ATmega329A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.5 85 °C 25°C 0.45 0.4 -40°C ICC [mA] 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-134.ATmega329A: Idle Supply Current vs. VCC (32kHz Watch Crystal) 10 9 85 °C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-5. PRR bit ATmega329A: Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 7µA 44µA 195µA PRUSART0 6.9µA 43.5µA 210µA PRSPI 6.6µA 47µA 205µA PRTIM1 7µA 47µA 206µA PRLCD 7.3µA 48µA 215µA Table 30-6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.4 Power-down Supply Current Figure 30-135.ATmega329A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2 85°C 1.8 1.6 ICC [uA] 1.4 1.2 1 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 30-136.ATmega329A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85°C 25°C -40°C 18 16 ICC [uA] 14 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.5 Power-save Supply Current Figure 30-137.ATmega329A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.6 Standby Supply Current Figure 30-138.ATmega329A Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 1.1 25°C 0.9 -40°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-139.ATmega329A: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC (mA) 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.7 Pin Pull-up Figure 30-140.ATmega329A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP [uA] 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VOP [V] Figure 30-141.ATmega329A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP [uA] 60 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-142.ATmega329A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP [uA] 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 30-143.ATmega329A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 140 120 IRESET [uA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-144.ATmega329A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 IRESET [uA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET [V] Figure 30-145.ATmega329A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET [uA] 30 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.8 Pin Driver Strength Figure 30-146.ATmega329A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40 °C 4.7 25 °C 4.65 85 °C 4.6 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 30-147.ATmega329A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40 °C 2.2 25 °C 2.1 85 °C 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-148.ATmega329A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40 °C 1.4 25 °C 85 °C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 30-149.ATmega329A: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-150.ATmega329A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH [V] 2.2 2 -40°C 1.8 25°C 1.6 85°C 1.4 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-151.ATmega329A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-152.ATmega329A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 30-153.ATmega329A. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85°C VOL [V] 1 0.8 25°C 0.6 -40°C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-154.ATmega329A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) VOL [V] 0.35 0.3 85°C 0.25 25°C 0.2 -40°C 0.15 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 30-155.ATmega329A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-156.ATmega329A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85°C 1 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-157.ATmega329A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.55 85°C 0.5 0.45 0.4 25°C VOL [V] 0.35 0.3 -40°C 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.9 Pin Threshold and Hysteresis Figure 30-158.ATmega329A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 -40 °C 25 °C 85 °C 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-159.ATmega329A. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 25 °C -40 °C 2.5 2.2 Threshold (V) 1.9 1.6 1.3 1 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-160.ATmega329A: I/O Pin Input Hysteresis vs. VCC 0.57 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.53 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-161.ATmega329A: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 25 °C -40 °C 2.2 85 °C Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-162.ATmega329A: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.5 -40 °C 85 °C 25 °C 2.25 Threshold (V) 2 1.75 1.5 1.25 1 0.75 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-163.ATmega329A: Reset Pin Input Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.10 BOD Thresholds and Analog Comparator Offset Figure 30-164.ATmega329A: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.325 4.3 Falling Vcc 4.275 4.25 4.225 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-165.ATmega329A: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.775 Rising Vcc BOD threshold [V] 2.75 2.725 2.7 Falling Vcc 2.675 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-166.ATmega329A: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.785 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-167.ATmega329A: Bandgap Voltage vs. VCC 1.12 1.115 Bandgap Voltage [V] 1.11 25°C 1.105 1.1 85°C 1.095 1.09 1.085 -40°C 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-168.ATmega329A: Bandgap Voltage vs. Temperature Bandgap Voltage [V] 1.115 1.11 1.8 V 2.7 V 4.0 V 1.105 5.5 V 1.1 1.095 1.09 1.085 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 30.3.11 Internal Oscillator Speed Figure 30-169.ATmega329A: Watchdog Oscillator Frequency vs. VCC 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-170.ATmega329A: Watchdog Oscillator Frequency vs. Temperature 1250 1200 FRC [kHz] 5.5 V 1150 5.0 V 4.5 V 4.0 V 1100 3.0 V 2.7 V 1050 1.8 V 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 30-171.ATmega329A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 8.2 8.1 FRC [MHz] 8 7.9 7.8 7.7 7.6 7.5 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-172.ATmega329A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-173.ATmega329A: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.12 Current Consumption of Peripheral Units Figure 30-174.ATmega329A: Brownout Detector Current vs. VCC 45 40 ICC [uA] 35 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-175.ATmega329A: Active Supply Current with ADC at 50kHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-176.ATmega329A: Active Supply Current with ADC at 200kHz vs. VCC 375 350 85°C -40°C 25°C 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-177.ATmega329A: Active Supply Current with ADC at 1MHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-178.ATmega329A: AREF External Reference Current vs. VCC 180 85°C 25°C -40°C 160 140 ICC [uA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-179.ATmega329A: Watchdog Timer Current vs. VCC 20 85°C 25°C -40°C 17.5 15 ICC [uA] 12.5 10 7.5 5 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-180.ATmega329A: Analog Comparator Current vs. VCC 90 -40°C 85°C 25°C 80 ICC [uA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-181.ATmega329A: Programming Current vs. VCC 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.3.13 Current Consumption in Reset and Reset Pulswidth Figure 30-182.ATmega329A: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 ICC [mA] 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 30-183.ATmega329A: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-184.ATmega329A: Minimum Reset Pulse Width vs. VCC 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4 30.4.1 ATmega329PA Active Supply Current Figure 30-185.ATmega329PA: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.4 5.5 V 1.2 5.0 V ICC [mA] 1 4.5 V 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 30-186.ATmega329PA: Active Supply Current vs. Frequency (1 - 20MHz) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-187.ATmega329PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25°C -40°C 6.5 6 5.5 ICC [mA] 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-188.ATmega329PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 85 °C 1.4 25°C -40°C ICC [mA] 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ICC [mA] Figure 30-189.ATmega329PA: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.4.2 Idle Supply Current Figure 30-190.ATmega329PA: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) ICC [MHz] 0.35 0.3 5.5 V 0.25 5.0 V 4.5 V 4.0 V 3.3 V 0.2 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-191.ATmega329PA: Idle Supply Current vs. Frequency (1 - 20MHz) 5 4.5 5.5 V 4 5.0 V ICC [MHz] 3.5 4.5 V 3 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 30-192.ATmega329PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 1.8 85 °C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-193.ATmega329PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.5 85 °C 25°C 0.45 0.4 -40°C ICC [mA] 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-194.ATmega329PA: Idle Supply Current vs. VCC (32kHz Watch Crystal) 10 9 85 °C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-7. PRR bit ATmega329PA: Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 7µA 44µA 195µA PRUSART0 6.9µA 43.5µA 210µA PRSPI 6.6µA 47µA 205µA PRTIM1 7µA 47µA 206µA PRLCD 7.3µA 48µA 215µA Table 30-8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.4 Power-down Supply Current Figure 30-195.ATmega329PA: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2 85°C 1.8 1.6 ICC [uA] 1.4 1.2 1 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 30-196.ATmega329PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85°C 25°C -40°C 18 16 ICC [uA] 14 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.5 Power-save Supply Current Figure 30-197.ATmega329PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.6 Standby Supply Current Figure 30-198.ATmega329PA Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 1.1 25°C 0.9 -40°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-199.ATmega329PA Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC (mA) 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.7 Pin Pull-up Figure 30-200.ATmega329PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP [uA] 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VOP [V] Figure 30-201.ATmega329PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP [uA] 60 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-202.ATmega329PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP [uA] 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 30-203.ATmega329PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 140 120 IRESET [uA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-204.ATmega329PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=2.7V) 70 60 IRESET [uA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET [V] Figure 30-205.ATmega329PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET [uA] 30 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.8 Pin Driver Strength Figure 30-206.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40 °C 4.7 25 °C 4.65 85 °C 4.6 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 30-207.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40 °C 2.2 25 °C 2.1 85 °C 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-208.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40 °C 1.4 25 °C 85 °C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 30-209.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-210.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH [V] 2.2 2 -40°C 1.8 25°C 1.6 85°C 1.4 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-211.ATmega329PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-212.ATmega329PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 30-213.ATmega329PA. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85°C VOL [V] 1 0.8 25°C 0.6 -40°C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-214.ATmega329PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) VOL [V] 0.35 0.3 85°C 0.25 25°C 0.2 -40°C 0.15 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 30-215.ATmega329PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-216.ATmega329PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85°C 1 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-217.ATmega329PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.55 85°C 0.5 0.45 0.4 25°C VOL [V] 0.35 0.3 -40°C 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.9 Pin Threshold and Hysteresis Figure 30-218.ATmega329PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 -40 °C 25 °C 85 °C 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-219.ATmega329PA. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 25 °C -40 °C 2.5 2.2 Threshold (V) 1.9 1.6 1.3 1 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-220.ATmega329PA: I/O Pin Input Hysteresis vs. VCC 0.57 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.53 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-221.ATmega329PA: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 25 °C -40 °C 2.2 85 °C Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-222.ATmega329PA: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.5 -40 °C 85 °C 25 °C 2.25 Threshold (V) 2 1.75 1.5 1.25 1 0.75 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-223.ATmega329PA: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.10 BOD Thresholds and Analog Comparator Offset Figure 30-224.ATmega329PA: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.325 4.3 Falling Vcc 4.275 4.25 4.225 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-225.ATmega329PA: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.775 Rising Vcc BOD threshold [V] 2.75 2.725 2.7 Falling Vcc 2.675 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-226.ATmega329PA: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.785 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-227.ATmega329PA: Bandgap Voltage vs. VCC 1.12 1.115 Bandgap Voltage [V] 1.11 25°C 1.105 1.1 85°C 1.095 1.09 1.085 -40°C 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-228.ATmega329PA: Bandgap Voltage vs. Temperature Bandgap Voltage [V] 1.115 1.11 1.8 V 2.7 V 4.0 V 1.105 5.5 V 1.1 1.095 1.09 1.085 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 30.4.11 Internal Oscillator Speed Figure 30-229.ATmega329PA: Watchdog Oscillator Frequency vs. VCC 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-230.ATmega329PA: Watchdog Oscillator Frequency vs. Temperature 1250 1200 FRC [kHz] 5.5 V 1150 5.0 V 4.5 V 4.0 V 1100 3.0 V 2.7 V 1050 1.8 V 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 30-231.ATmega329PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 8.2 8.1 FRC [MHz] 8 7.9 7.8 7.7 7.6 7.5 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-232.ATmega329PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-233.ATmega329PA: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.12 Current Consumption of Peripheral Units Figure 30-234.ATmega329PA: Brownout Detector Current vs. VCC 45 40 ICC [uA] 35 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-235.ATmega329PA: Active Supply Current with ADC at 50kHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-236.ATmega329PA: Active Supply Current with ADC at 200kHz vs. VCC 375 350 85°C -40°C 25°C 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-237.ATmega329PA: Active Supply Current with ADC at 1MHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-238.ATmega329PA: AREF External Reference Current vs. VCC 180 85°C 25°C -40°C 160 140 ICC [uA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-239.ATmega329PA: Watchdog Timer Current vs. VCC 20 85°C 25°C -40°C 17.5 15 ICC [uA] 12.5 10 7.5 5 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-240.ATmega329PA: Analog Comparator Current vs. VCC 90 -40°C 85°C 25°C 80 ICC [uA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-241.ATmega329PA: Programming Current vs. VCC 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.4.13 Current Consumption in Reset and Reset Pulswidth Figure 30-242.ATmega329PA: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 ICC [mA] 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 30-243.ATmega329PA: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-244.ATmega329PA: Minimum Reset Pulse Width vs. VCC 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.5 30.5.1 ATmega3290A Active Supply Current Figure 30-245.ATmega3290A: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.4 5.5 V 1.2 5.0 V ICC [mA] 1 4.5 V 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 30-246.ATmega3290A: Active Supply Current vs. Frequency (1 - 20MHz) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-247.ATmega3290A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25°C -40°C 6.5 6 5.5 ICC [mA] 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-248.ATmega3290A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 85 °C 1.4 25°C -40°C ICC [mA] 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ICC [mA] Figure 30-249.ATmega3290A: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.5.2 Idle Supply Current Figure 30-250.ATmega3290A: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) ICC [MHz] 0.35 0.3 5.5 V 0.25 5.0 V 4.5 V 4.0 V 3.3 V 0.2 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-251.ATmega3290A: Idle Supply Current vs. Frequency (1 - 20MHz) 5 4.5 5.5 V 4 5.0 V ICC [MHz] 3.5 4.5 V 3 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 30-252.ATmega3290A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 1.8 85 °C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-253.ATmega3290A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.5 85 °C 25°C 0.45 0.4 -40°C ICC [mA] 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-254.ATmega3290A: Idle Supply Current vs. VCC (32kHz Watch Crystal) 10 9 85 °C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-9. PRR bit ATmega3290A: Additional Current Consumption for the different I/O modules (absolute values) Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 7µA 44µA 195µA PRUSART0 6.9µA 43.5µA 210µA PRSPI 6.6µA 47µA 205µA PRTIM1 7µA 47µA 206µA PRLCD 7.3µA 48µA 215µA Table 30-10.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.5.4 Power-down Supply Current Figure 30-255.ATmega3290A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2 85°C 1.8 1.6 ICC [uA] 1.4 1.2 1 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 30-256.ATmega3290A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85°C 25°C -40°C 18 16 ICC [uA] 14 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.5.5 Power-save Supply Current Figure 30-257.ATmega3290A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2. 30.5.6 Standby Supply Current Figure 30-258.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-259.ATmega3290A: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC (mA) 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.07 0.05 0.03 0.01 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.5.7 Pin Pull-up Figure 30-260.ATmega3290A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP [uA] 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-261.ATmega3290A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP [uA] 60 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.5 3 VOP [V] Figure 30-262.ATmega3290A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP [uA] 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-263.ATmega3290A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 140 120 IRESET [uA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET [V] Figure 30-264.ATmega3290A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=2.7V) 70 60 IRESET [uA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-265.ATmega3290A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=1.8V) 40 35 IRESET [uA] 30 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VRESET [V] 30.5.8 Pin Driver Strength Figure 30-266.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40 °C 4.7 25 °C 4.65 85 °C 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-267.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40 °C 2.2 25 °C 2.1 85 °C 2 1.9 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 30-268.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40 °C 1.4 25 °C 85 °C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-269.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.3 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-270.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH [V] 2.2 2 -40°C 1.8 25°C 1.6 85°C 1.4 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-271.ATmega3290A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH [mA] Figure 30-272.ATmega3290A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-273.ATmega3290A. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85°C VOL [V] 1 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 30-274.ATmega3290A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) VOL [V] 0.35 0.3 85°C 0.25 25°C 0.2 -40°C 0.15 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-275.ATmega3290A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-276.ATmega3290A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85°C 1 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-277.ATmega3290A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.55 85°C 0.5 0.45 0.4 25°C VOL [V] 0.35 0.3 -40°C 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 IOL [mA] 30.5.9 Pin Threshold and Hysteresis Figure 30-278.ATmega3290A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 -40 °C 25 °C 85 °C 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-279.ATmega3290A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 25 °C -40 °C 2.5 2.2 Threshold (V) 1.9 1.6 1.3 1 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-280.ATmega3290A: I/O Pin Input Hysteresis vs. VCC 0.57 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.53 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-281.ATmega3290A: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 25 °C -40 °C 2.2 85 °C Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-282.ATmega3290A: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.5 -40 °C 85 °C 25 °C 2.25 Threshold (V) 2 1.75 1.5 1.25 1 0.75 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-283.ATmega3290A: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.5.10 BOD Thresholds and Analog Comparator Offset Figure 30-284.ATmega3290A: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.325 4.3 Falling Vcc 4.275 4.25 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-285.ATmega3290A: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.775 Rising Vcc BOD threshold [V] 2.75 2.725 2.7 Falling Vcc 2.675 2.65 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-286.ATmega3290A: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-287.ATmega3290A: Bandgap Voltage vs. VCC 1.12 1.115 Bandgap Voltage [V] 1.11 25°C 1.105 1.1 85°C 1.095 1.09 1.085 -40°C 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc [V] Figure 30-288.ATmega3290A: Bandgap Voltage vs. Temperature Bandgap Voltage [V] 1.115 1.11 1.8 V 2.7 V 4.0 V 1.105 5.5 V 1.1 1.095 1.09 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.5.11 Internal Oscillator Speed Figure 30-289.ATmega3290A: Watchdog Oscillator Frequency vs. VCC 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-290.ATmega3290A: Watchdog Oscillator Frequency vs. Temperature 1250 1200 FRC [kHz] 5.5 V 1150 5.0 V 4.5 V 4.0 V 1100 3.0 V 2.7 V 1050 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-291.ATmega3290A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 8.2 8.1 FRC [MHz] 8 7.9 7.8 7.7 7.6 7.5 7.4 -40 -20 0 20 40 60 80 Temperature [°C] Figure 30-292.ATmega3290A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-293.ATmega3290A: Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 85 °C 25 °C -40 °C 14 12 FRC [MHz] 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 30.5.12 Current Consumption of Peripheral Units Figure 30-294.ATmega3290A: Brownout Detector Current vs. VCC 45 40 ICC [uA] 35 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-295.ATmega3290A: Active Supply Current with ADC at 50kHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-296.ATmega3290A: Active Supply Current with ADC at 200kHz vs. VCC 375 350 85°C -40°C 25°C 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-297.ATmega3290A: Active Supply Current with ADC at 1MHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-298.ATmega3290A: AREF External Reference Current vs. VCC 180 85°C 25°C -40°C 160 140 ICC [uA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-299.ATmega3290A: Watchdog Timer Current vs. VCC 20 85°C 25°C -40°C 17.5 15 ICC [uA] 12.5 10 7.5 5 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-300.ATmega3290A: Analog Comparator Current vs. VCC 90 -40°C 85°C 25°C 80 ICC [uA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-301.ATmega3290A: Programming Current vs. VCC 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.5.13 Current Consumption in Reset and Reset Pulswidth Figure 30-302.ATmega3290A: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 ICC [mA] 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-303.ATmega3290A: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.5 5.5 V ICC [mA] 2 5.0 V 4.5 V 1.5 4.0 V 1 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 30-304.ATmega3290A: Minimum Reset Pulse Width vs. VCC 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6 30.6.1 ATmega3290PA Active Supply Current Figure 30-305.ATmega3290PA: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.4 5.5 V 1.2 5.0 V ICC [mA] 1 4.5 V 4.0 V 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] ICC [mA] Figure 30-306.ATmega3290PA: Active Supply Current vs. Frequency (1 - 20MHz) 14 5.5 V 12 5.0 V 10 4.5 V 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-307.ATmega3290PA: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25°C -40°C 6.5 6 5.5 ICC [mA] 5 4.5 4 3.5 3 2.5 2 1.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-308.ATmega3290PA: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 85 °C 1.4 25°C -40°C ICC [mA] 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P ICC [mA] Figure 30-309.ATmega3290PA: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 85°C 25°C -40°C 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.6.2 Idle Supply Current Figure 30-310.ATmega3290PA: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) ICC [MHz] 0.35 0.3 5.5 V 0.25 5.0 V 4.5 V 4.0 V 3.3 V 0.2 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-311.ATmega3290PA: Idle Supply Current vs. Frequency (1 - 20MHz) 5 4.5 5.5 V 4 5.0 V ICC [MHz] 3.5 4.5 V 3 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [V] Figure 30-312.ATmega3290PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 1.8 85 °C 25°C 1.6 -40°C ICC [mA] 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-313.ATmega3290PA: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.5 85 °C 25°C 0.45 0.4 -40°C ICC [mA] 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-314.ATmega3290PA: Idle Supply Current vs. VCC (32kHz Watch Crystal) 10 9 85 °C 8 25°C -40°C ICC [mA] 7 6 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] 30.6.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-11. ATmega3290PA: Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 7µA 44µA 195µA PRUSART0 6.9µA 43.5µA 210µA PRSPI 6.6µA 47µA 205µA PRTIM1 7µA 47µA 206µA PRLCD 7.3µA 48µA 215µA Table 30-12.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.4 Power-down Supply Current Figure 30-315.ATmega3290PA Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2 85°C 1.8 1.6 ICC [uA] 1.4 1.2 1 0.8 0.6 0.4 25°C -40°C 0.2 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VCC [V] Figure 30-316.ATmega3290PA: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85°C 25°C -40°C 18 16 ICC [uA] 14 12 10 8 6 4 2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.5 Power-save Supply Current Figure 30-317.ATmega3290PA: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 25°C 1.1 -40°C 0.9 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] The differential current consumption between Power-save with WD disabled and 32kHz TOSC represents the current drawn by Timer/Counter2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.6 Standby Supply Current Figure 30-318.ATmega3290PA Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 85°C 2.1 1.9 ICC [mA] 1.7 1.5 1.3 1.1 25°C 0.9 -40°C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-319.ATmega3290PA: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.13 6MHz_xtal 6MHz_res 0.11 4MHz_xtal 4MHz_res ICC (mA) 0.09 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.7 Pin Pull-up Figure 30-320.ATmega3290PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP [uA] 100 80 60 40 -40 °C 25 °C 85 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VOP [V] Figure 30-321.ATmega3290PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 70 IOP [uA] 60 50 40 30 20 -40 °C 25 °C 85 °C 10 0 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-322.ATmega3290PA: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP [uA] 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOP [V] Figure 30-323.ATmega3290PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=5V) 140 120 IRESET [uA] 100 80 60 40 20 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-324.ATmega3290PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=2.7V) 70 60 IRESET [uA] 50 40 30 20 10 -40 °C 25 °C 85 °C 0 0 0.5 1 1.5 2 2.5 3 VRESET [V] Figure 30-325.ATmega3290PA: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC=1.8V) 40 35 IRESET [uA] 30 25 20 15 10 -40 °C 25 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.8 Pin Driver Strength Figure 30-326.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5.05 5 4.95 VOH [V] 4.9 4.85 4.8 4.75 -40 °C 4.7 4.65 25 °C 4.6 85 °C 0 1 2 3 4 5 6 7 8 9 10 IOH [mA] Figure 30-327.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.8 2.7 2.6 VOH [V] 2.5 2.4 2.3 -40 °C 2.2 25 °C 2.1 85 °C 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-328.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.9 1.8 VOH [V] 1.7 1.6 1.5 -40 °C 1.4 25 °C 85 °C 1.3 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH [mA] Figure 30-329.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5.1 5 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-330.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH [V] 2.2 2 -40°C 1.8 25°C 1.6 85°C 1.4 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 30-331.ATmega3290PA: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.7 VOH [V] 1.6 1.5 -40°C 25°C 1.4 85°C 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-332.ATmega3290PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL [mA] Figure 30-333.ATmega3290PA. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85°C VOL [V] 1 0.8 25°C 0.6 -40°C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-334.ATmega3290PA: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) VOL [V] 0.35 0.3 85°C 0.25 25°C 0.2 -40°C 0.15 0.1 0.05 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL [mA] Figure 30-335.ATmega3290PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) VOL [V] 0.7 0.6 85°C 0.5 25°C 0.4 -40°C 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-336.ATmega3290PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85°C 1 25°C VOL [V] 0.8 -40°C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 30-337.ATmega3290PA: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.55 85°C 0.5 0.45 0.4 25°C VOL [V] 0.35 0.3 -40°C 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.9 Pin Threshold and Hysteresis Figure 30-338.ATmega3290PA: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 -40 °C 25 °C 85 °C 2.7 Threshold (V) 2.4 2.1 1.8 1.5 1.2 0.9 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-339.ATmega3290PA. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 85 °C 25 °C -40 °C 2.5 2.2 Threshold (V) 1.9 1.6 1.3 1 0.7 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-340.ATmega3290PA: I/O Pin Input Hysteresis vs. VCC 0.57 -40 °C 25 °C 85 °C Input Hysteresis (mV) 0.53 0.49 0.45 0.41 0.37 0.33 0.29 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-341.ATmega3290PA: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.4 25 °C -40 °C 2.2 85 °C Threshold (V) 2 1.8 1.6 1.4 1.2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-342.ATmega3290PA: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.5 -40 °C 85 °C 25 °C 2.25 Threshold (V) 2 1.75 1.5 1.25 1 0.75 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-343.ATmega3290PA: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.10 BOD Thresholds and Analog Comparator Offset Figure 30-344.ATmega3290PA: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.35 Rising Vcc BOD threshold [V] 4.325 4.3 Falling Vcc 4.275 4.25 4.225 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-345.ATmega3290PA: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.775 Rising Vcc BOD threshold [V] 2.75 2.725 2.7 Falling Vcc 2.675 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-346.ATmega3290PA: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.835 Rising Vcc BOD threshold [V] 1.825 1.815 Falling Vcc 1.805 1.795 1.785 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 30-347.ATmega3290PA: Bandgap Voltage vs. VCC 1.12 1.115 Bandgap Voltage [V] 1.11 25°C 1.105 1.1 85°C 1.095 1.09 1.085 -40°C 1.08 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-348.ATmega3290PA: Bandgap Voltage vs. Temperature Bandgap Voltage [V] 1.115 1.11 1.8 V 2.7 V 4.0 V 1.105 5.5 V 1.1 1.095 1.09 1.085 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] 30.6.11 Internal Oscillator Speed Figure 30-349.ATmega3290PA: Watchdog Oscillator Frequency vs. VCC 1225 1200 25°C -40°C 85°C 1175 FRC [kHz] 1150 1125 1100 1075 1050 1025 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-350.ATmega3290PA: Watchdog Oscillator Frequency vs. Temperature 1250 1200 FRC [kHz] 5.5 V 1150 5.0 V 4.5 V 4.0 V 1100 3.0 V 2.7 V 1050 1.8 V 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 30-351.ATmega3290PA: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.3 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 8.2 8.1 FRC [MHz] 8 7.9 7.8 7.7 7.6 7.5 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-352.ATmega3290PA: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.3 85°C 8.2 8.1 25°C FRC [MHz] 8 7.9 7.8 7.7 -40°C 7.6 7.5 7.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-353.ATmega3290PA: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.12 Current Consumption of Peripheral Units Figure 30-354.ATmega3290PA: Brownout Detector Current vs. VCC 45 40 ICC [uA] 35 30 85°C 25°C -40°C 25 20 15 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-355.ATmega3290PA: Active Supply Current with ADC at 50kHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-356.ATmega3290PA: Active Supply Current with ADC at 200kHz vs. VCC 375 350 85°C -40°C 25°C 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-357.ATmega3290PA: Active Supply Current with ADC at 1MHz vs. VCC 375 -40°C 85°C 25°C 350 325 ICC [uA] 300 275 250 225 200 175 150 125 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-358.ATmega3290PA: AREF External Reference Current vs. VCC 180 85°C 25°C -40°C 160 140 ICC [uA] 120 100 80 60 40 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-359.ATmega3290PA: Watchdog Timer Current vs. VCC 20 85°C 25°C -40°C 17.5 15 ICC [uA] 12.5 10 7.5 5 2.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-360.ATmega3290PA: Analog Comparator Current vs. VCC 90 -40°C 85°C 25°C 80 ICC [uA] 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 30-361.ATmega3290PA: Programming Current vs. VCC 14 -40°C 25°C 12 85°C ICC [mA] 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.6.13 Current Consumption in Reset and Reset Pulswidth Figure 30-362.ATmega3290PA: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up 0.16 ICC [mA] 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 0.08 4.0 V 0.06 3.3 V 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 30-363.ATmega3290PA: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-364.ATmega3290PA: Minimum Reset Pulse Width vs. VCC 2500 2250 2000 Pulsewidth [ns] 1750 1500 1250 1000 750 85°C 25°C -40°C 500 250 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7 30.7.1 ATmega649A Active Supply Current Figure 30-365.ATmega649A: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.2 5.5 V 5.0 V 1 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-366.ATmega649A: Active Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-367.ATmega649A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25 °C -45 °C 6 ICC (mA) 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-368.ATmega649A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.45 25 °C 85 °C -45 °C 0.4 ICC (mA) 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-369.ATmega649A: Active Supply Current vs. VCC (32kHz Watch Crystal) 85 °C 25 °C -45 °C 40 36 32 ICC (mA) 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.7.2 Idle Supply Current Figure 30-370.ATmega649A: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) 0.3 5.5 V 0.27 5.0 V 4.5 V 0.24 ICC (mA) 0.21 0.18 4.0 V 0.15 3.3 V 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-371.ATmega649A: Idle Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-372.ATmega649A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 85 °C 25 °C -45 °C 1.8 1.6 ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-373.ATmega649A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-374.ATmega649A: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9.5 85 °C 8.5 25 °C -45 °C 7.5 ICC (mA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-13. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 23.75µA 212.1µA 938µA PRUSART0 36.7µA 210.4µA 939µA PRSPI 32.1µA 213µA 940µA PRTIM1 24.2µA 217µA 940µA PRLCD 27.3µA 208.8µA 935µA Table 30-14.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.4 Power-down Supply Current Figure 30-375.ATmega649A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 85 °C 2.2 2 1.8 ICC (uA) 1.6 1.4 1.2 1 0.8 25 °C -45 °C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-376.ATmega649A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-377.ATmega649A: Power-down Supply Current vs. VCC (32kHz Watch Crystal) 1.5 85 °C 1.3 ICC (mA) 1.1 0.9 0.7 0.5 0.3 25 °C -45 °C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.7.5 Power-save Supply Current Figure 30-378.ATmega649A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.6 Standby Supply Current Figure 30-379.ATmega649A Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-380.ATmega649A: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 ICC (mA) 0.085 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.7 Pin Pull-up Figure 30-381.ATmega649A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 30-382.ATmega649A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 0 85 °C -45 °C 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-383.ATmega649A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 °C 85 °C 1.8 -45 °C VOP (V) Figure 30-384.ATmega649A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET (uA) 90 75 60 45 30 25 °C -45 °C 85 °C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-385.ATmega649A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 54 48 IRESET (uA) 42 36 30 24 18 12 25 °C -45 °C 85 °C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) Figure 30-386.ATmega649A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C -45 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.8 Pin Driver Strength Figure 30-387.ATmega649A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5 4.95 4.9 VOH (V) 4.85 4.8 4.75 -45 °C 4.7 4.65 25 °C 4.6 85 °C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-388.ATmega649A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.7 2.6 2.5 VOH (V) 2.4 2.3 -45 °C 2.2 2.1 25 °C 2 85 °C 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-389.ATmega649A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 1.4 25 °C 1.3 85 °C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH (mA) Figure 30-390.ATmega649A: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 85 °C 4.4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-391.ATmega649A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 1.4 85 °C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-392.ATmega649A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 1.5 -45 °C 1.45 1.4 25 °C 85 °C 1.35 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-393.ATmega649A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) -45 °C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-394.ATmega649A. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-395.ATmega649A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.32 85 °C 25 °C 0.28 0.24 -45 °C VOL (V) 0.2 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL (mA) Figure 30-396.ATmega649A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 25 °C 0.5 -45 °C VOL (V) 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-397.ATmega649A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C 1 25 °C VOL (V) 0.8 -45 °C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-398.ATmega649A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.45 25 °C 0.4 0.35 -45 °C VOL (V) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.9 Pin Threshold and Hysteresis Figure 30-399.ATmega649A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-400.ATmega649A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.4 85 °C 25 °C -45 °C 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-401.ATmega649A: I/O Pin Input Hysteresis vs. VCC 0.6 -45 °C 0.55 Input Hysteresis (V) -45 °C 0.5 25 °C 0.45 0.4 85 °C 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-402.ATmega649A: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) -45 °C 25 °C 85 °C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-403.ATmega649A: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 85 °C 25 °C -45 °C 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-404.ATmega649A: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.10 BOD Thresholds and Analog Comparator Offset Figure 30-405.ATmega649A: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.41 Rising Vcc BOD threshold (V) 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-406.ATmega649A: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.795 2.785 Rising Vcc 2.775 BOD threshold (V) 2.765 2.755 2.745 2.735 Falling Vcc 2.725 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-407.ATmega649A: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.845 Rising Vcc 1.84 BOD threshold (V) 1.835 1.83 1.825 Falling Vcc 1.82 1.815 1.81 1.805 1.8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-408.ATmega649A: Bandgap Voltage vs. VCC 1.103 1.101 Bandgap Voltage (V) 1.099 25 °C 1.097 85 °C 1.095 1.093 1.091 1.089 1.087 1.085 -45 °C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-409.ATmega649A: Bandgap Voltage vs. Temperature 1.11 1.8 V 1.108 3.3 V Bandgap Voltage (V) 1.106 5.0 V 1.104 5.5 V 1.102 1.1 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) 30.7.11 Internal Oscillator Speed Figure 30-410.ATmega649A: Watchdog Oscillator Frequency vs. VCC 1290 -45 °C 25 °C 1260 85 °C 1230 FRC (kHz) 1200 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-411.ATmega649A: Watchdog Oscillator Frequency vs. Temperature 1290 1260 5.5 V 1230 5.0 V FRC (kHz) 1200 4.5 V 4.0 V 3.3 V 2.7 V 1170 1140 1110 1080 1.8 V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-412.ATmega649A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 3.3 V 2.7 V 8.2 8.1 8 FRC (MHz) 7.9 1.8 V 7.8 7.7 7.6 7.5 7.4 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-413.ATmega649A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C 8 FRC (MHz) 7.9 -45 °C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-414.ATmega649A: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.12 Current Consumption of Peripheral Units Figure 30-415.ATmega649A: Brownout Detector Current vs. VCC 42 39 36 ICC (uA) 33 30 27 85 °C 25 °C -45 °C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-416.ATmega649A: Active Supply Current with ADC at 50kHz vs. VCC 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-417.ATmega649A: Active Supply Current with ADC at 200kHz vs. VCC 360 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-418.ATmega649A: Active Supply Current with ADC at 1MHz vs. VCC 340 85 °C 25 °C -45 °C 310 ICC (uA) 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-419.ATmega649A: AREF External Reference Current vs. VCC 170 85 °C 25 °C -45 °C 155 140 ICC (uA) 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-420.ATmega649A: Watchdog Timer Current vs. VCC 18 85 °C 25 °C -45 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-421.ATmega649A: Analog Comparator Current vs. VCC 110 25 °C 100 85 °C 90 ICC (uA) 80 -45 °C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-422.ATmega649A: Programming Current vs. VCC 20 -45 °C 18 16 ICC (mA) 14 25 °C 12 10 85 °C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.7.13 Current Consumption in Reset and Reset Pulswidth Figure 30-423.ATmega649A: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 0.16 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-424.ATmega649A: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-425.ATmega649A: Minimum Reset Pulse Width vs. VCC 2400 2100 Pulsewidth (ns) 1800 1500 1200 900 600 85 °C 25 °C -45 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8 30.8.1 ATmega649P Active Supply Current Figure 30-426.ATmega649P: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.2 5.5 V 5.0 V 1 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-427.ATmega649P: Active Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-428.ATmega649P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25 °C -45 °C 6 ICC (mA) 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-429.ATmega649P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-430.ATmega649P: Active Supply Current vs. VCC (32kHz Watch Crystal) 85 °C 25 °C -45 °C 40 36 32 ICC (mA) 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.8.2 Idle Supply Current Figure 30-431.ATmega649P: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) 0.3 5.5 V 0.27 5.0 V 4.5 V 0.24 ICC (mA) 0.21 0.18 4.0 V 0.15 3.3 V 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-432.ATmega649P: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-433.ATmega649P: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 85 °C 25 °C -45 °C 1.8 1.6 ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-434.ATmega649P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.45 25 °C 85 °C -45 °C 0.4 ICC (mA) 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-435.ATmega649P: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9.5 85 °C 8.5 25 °C -45 °C 7.5 ICC (mA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.8.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-15. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 23.75µA 212.1µA 938µA PRUSART0 36.7µA 210.4µA 939µA PRSPI 32.1µA 213µA 940µA PRTIM1 24.2µA 217µA 940µA PRLCD 27.3µA 208.8µA 935µA Table 30-16.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.4 Power-down Supply Current Figure 30-436.ATmega649P: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 85 °C 2.2 2 1.8 ICC (uA) 1.6 1.4 1.2 1 0.8 25 °C -45 °C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-437.ATmega649P: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-438.ATmega649P: Power-down Supply Current vs. VCC (32kHz Watch Crystal) 1.5 85 °C 1.3 ICC (mA) 1.1 0.9 0.7 0.5 0.3 25 °C -45 °C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.8.5 Power-save Supply Current Figure 30-439.ATmega649P: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.6 Standby Supply Current Figure 30-440.ATmega649P Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-441.ATmega649P: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 ICC (mA) 0.085 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.7 Pin Pull-up Figure 30-442.ATmega649P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 30-443.ATmega649P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 0 85 °C -45 °C 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-444.ATmega649P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 °C 85 °C 1.8 -45 °C VOP (V) Figure 30-445.ATmega649P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET (uA) 90 75 60 45 30 25 °C -45 °C 85 °C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-446.ATmega649P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 54 48 IRESET (uA) 42 36 30 24 18 12 25 °C -45 °C 85 °C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) Figure 30-447.ATmega649P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C -45 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.8 Pin Driver Strength Figure 30-448.ATmega649P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5 4.95 4.9 VOH (V) 4.85 4.8 4.75 -45 °C 4.7 4.65 25 °C 4.6 85 °C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-449.ATmega649P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.7 2.6 2.5 VOH (V) 2.4 2.3 -45 °C 2.2 2.1 25 °C 2 85 °C 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-450.ATmega649P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 1.4 25 °C 1.3 85 °C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH (mA) Figure 30-451.ATmega649P: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 85 °C 4.4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-452.ATmega649P: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 1.4 85 °C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-453.ATmega649P: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 1.5 -45 °C 1.45 1.4 25 °C 85 °C 1.35 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-454.ATmega649P: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) -45 °C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-455.ATmega649P. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-456.ATmega649P: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.32 85 °C 25 °C 0.28 0.24 -45 °C VOL (V) 0.2 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL (mA) Figure 30-457.ATmega649P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 25 °C 0.5 -45 °C VOL (V) 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-458.ATmega649P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C 1 25 °C VOL (V) 0.8 -45 °C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-459.ATmega649P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.45 25 °C 0.4 0.35 -45 °C VOL (V) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.9 Pin Threshold and Hysteresis Figure 30-460.ATmega649P: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-461.ATmega649P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.4 85 °C 25 °C -45 °C 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-462.ATmega649P: I/O Pin Input Hysteresis vs. VCC 0.6 -45 °C 0.55 Input Hysteresis (V) -45 °C 0.5 25 °C 0.45 0.4 85 °C 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-463.ATmega649P: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) -45 °C 25 °C 85 °C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-464.ATmega649P: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 85 °C 25 °C -45 °C 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-465.ATmega649P: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.10 BOD Thresholds and Analog Comparator Offset Figure 30-466.ATmega649P: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.41 Rising Vcc BOD threshold (V) 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-467.ATmega649P: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.795 2.785 Rising Vcc 2.775 BOD threshold (V) 2.765 2.755 2.745 2.735 Falling Vcc 2.725 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-468.ATmega649P: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.845 Rising Vcc 1.84 BOD threshold (V) 1.835 1.83 1.825 Falling Vcc 1.82 1.815 1.81 1.805 1.8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-469.ATmega649P: Bandgap Voltage vs. VCC 1.103 1.101 Bandgap Voltage (V) 1.099 25 °C 1.097 85 °C 1.095 1.093 1.091 1.089 1.087 1.085 -45 °C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-470.ATmega649P: Bandgap Voltage vs. Temperature 1.11 1.8 V 1.108 3.3 V Bandgap Voltage (V) 1.106 5.0 V 1.104 5.5 V 1.102 1.1 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) 30.8.11 Internal Oscillator Speed Figure 30-471.ATmega649P: Watchdog Oscillator Frequency vs. VCC 1290 -45 °C 25 °C 1260 85 °C 1230 FRC (kHz) 1200 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-472.ATmega649P: Watchdog Oscillator Frequency vs. Temperature 1290 1260 5.5 V 1230 5.0 V FRC (kHz) 1200 4.5 V 4.0 V 3.3 V 2.7 V 1170 1140 1110 1080 1.8 V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-473.ATmega649P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 3.3 V 2.7 V 8.2 8.1 8 FRC (MHz) 7.9 1.8 V 7.8 7.7 7.6 7.5 7.4 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-474.ATmega649P: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C 8 FRC (MHz) 7.9 -45 °C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-475.ATmega649P: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.12 Current Consumption of Peripheral Units Figure 30-476.ATmega649P: Brownout Detector Current vs. VCC 42 39 36 ICC (uA) 33 30 27 85 °C 25 °C -45 °C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-477.ATmega649P: Active Supply Current with ADC at 50kHz vs. VCC 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-478.ATmega649P: Active Supply Current with ADC at 200kHz vs. VCC 360 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-479.ATmega649P: Active Supply Current with ADC at 1MHz vs. VCC 340 85 °C 25 °C -45 °C 310 ICC (uA) 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-480.ATmega649P: AREF External Reference Current vs. VCC 170 85 °C 25 °C -45 °C 155 140 ICC (uA) 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-481.ATmega649P: Watchdog Timer Current vs. VCC 18 85 °C 25 °C -45 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-482.ATmega649P: Analog Comparator Current vs. VCC 110 25 °C 100 85 °C 90 ICC (uA) 80 -45 °C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-483.ATmega649P: Programming Current vs. VCC 20 -45 °C 18 16 ICC (mA) 14 25 °C 12 10 85 °C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.8.13 Current Consumption in Reset and Reset Pulswidth Figure 30-484.ATmega649P: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) ICC (mA) 0.16 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-485.ATmega649P: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-486.ATmega649P: Minimum Reset Pulse Width vs. VCC 2400 2100 Pulsewidth (ns) 1800 1500 1200 900 600 85 °C 25 °C -45 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9 30.9.1 ATmega6490A Active Supply Current Figure 30-487.ATmega6490A: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.2 5.5 V 5.0 V 1 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-488.ATmega6490A: Active Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-489.ATmega6490A: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25 °C -45 °C 6 ICC (mA) 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-490.ATmega6490A: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.45 25 °C 85 °C -45 °C 0.4 ICC (mA) 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-491.ATmega6490A: Active Supply Current vs. VCC (32kHz Watch Crystal) 85 °C 25 °C -45 °C 40 36 32 ICC (mA) 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.9.2 Idle Supply Current Figure 30-492.ATmega6490A: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) 0.3 5.5 V 0.27 5.0 V 4.5 V 0.24 ICC (mA) 0.21 0.18 4.0 V 0.15 3.3 V 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-493.ATmega6490A: Idle Supply Current vs. Frequency (1 - 20MHz) 4.5 5.5 V 4 5.0 V 3.5 4.5 V ICC (mA) 3 2.5 2 4.0 V 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-494.ATmega6490A: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 85 °C 25 °C -45 °C 1.8 1.6 ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-495.ATmega6490A: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-496.ATmega6490A: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9.5 85 °C 8.5 25 °C -45 °C 7.5 ICC (mA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.9.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-17. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 23.75µA 212.1µA 938µA PRUSART0 36.7µA 210.4µA 939µA PRSPI 32.1µA 213µA 940µA PRTIM1 24.2µA 217µA 940µA PRLCD 27.3µA 208.8µA 935µA Table 30-18.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.4 Power-down Supply Current Figure 30-497.ATmega6490A: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 85 °C 2.2 2 1.8 ICC (uA) 1.6 1.4 1.2 1 0.8 25 °C -45 °C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-498.ATmega6490A: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-499.ATmega6490A: Power-down Supply Current vs. VCC (32kHz Watch Crystal) 1.5 85 °C 1.3 ICC (mA) 1.1 0.9 0.7 0.5 0.3 25 °C -45 °C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.9.5 Power-save Supply Current Figure 30-500.ATmega6490A: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.6 Standby Supply Current Figure 30-501.ATmega6490A Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-502.ATmega6490A: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 ICC (mA) 0.085 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.7 Pin Pull-up Figure 30-503.ATmega6490A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 30-504.ATmega6490A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 0 85 °C -45 °C 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-505.ATmega6490A: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 °C 85 °C 1.8 -45 °C VOP (V) Figure 30-506.ATmega6490A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET (uA) 90 75 60 45 30 25 °C -45 °C 85 °C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-507.ATmega6490A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 54 48 IRESET (uA) 42 36 30 24 18 12 25 °C -45 °C 85 °C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) Figure 30-508.ATmega6490A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C -45 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.8 Pin Driver Strength Figure 30-509.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 5V) 5 4.95 4.9 VOH (V) 4.85 4.8 4.75 -45 °C 4.7 4.65 25 °C 4.6 85 °C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-510.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 2.7V) 2.7 2.6 2.5 VOH (V) 2.4 2.3 -45 °C 2.2 2.1 25 °C 2 85 °C 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-511.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC = 1.8V) 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 1.4 25 °C 1.3 85 °C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH (mA) Figure 30-512.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 85 °C 4.4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-513.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 1.4 85 °C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-514.ATmega6490A: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 1.5 -45 °C 1.45 1.4 25 °C 85 °C 1.35 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-515.ATmega6490A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) -45 °C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-516.ATmega6490A. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-517.ATmega6490A: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.32 85 °C 25 °C 0.28 0.24 -45 °C VOL (V) 0.2 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL (mA) Figure 30-518.ATmega6490A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 25 °C 0.5 -45 °C VOL (V) 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-519.ATmega6490A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C 1 25 °C VOL (V) 0.8 -45 °C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-520.ATmega6490A: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.45 25 °C 0.4 0.35 -45 °C VOL (V) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.9 Pin Threshold and Hysteresis Figure 30-521.ATmega6490A: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-522.ATmega6490A: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.4 85 °C 25 °C -45 °C 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-523.ATmega6490A: I/O Pin Input Hysteresis vs. VCC 0.6 -45 °C 0.55 Input Hysteresis (V) -45 °C 0.5 25 °C 0.45 0.4 85 °C 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-524.ATmega6490A: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) -45 °C 25 °C 85 °C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-525.ATmega6490A: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 85 °C 25 °C -45 °C 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-526.ATmega6490A: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.10 BOD Thresholds and Analog Comparator Offset Figure 30-527.ATmega6490A: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.41 Rising Vcc BOD threshold (V) 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-528.ATmega6490A: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.795 2.785 Rising Vcc 2.775 BOD threshold (V) 2.765 2.755 2.745 2.735 Falling Vcc 2.725 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-529.ATmega6490A: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.845 Rising Vcc 1.84 BOD threshold (V) 1.835 1.83 1.825 Falling Vcc 1.82 1.815 1.81 1.805 1.8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-530.ATmega6490A: Bandgap Voltage vs. VCC 1.103 1.101 Bandgap Voltage (V) 1.099 25 °C 1.097 85 °C 1.095 1.093 1.091 1.089 1.087 1.085 -45 °C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-531.ATmega6490A: Bandgap Voltage vs. Temperature 1.11 1.8 V 1.108 3.3 V Bandgap Voltage (V) 1.106 5.0 V 1.104 5.5 V 1.102 1.1 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) 30.9.11 Internal Oscillator Speed Figure 30-532.ATmega6490A: Watchdog Oscillator Frequency vs. VCC 1290 -45 °C 25 °C 1260 85 °C 1230 FRC (kHz) 1200 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-533.ATmega6490A: Watchdog Oscillator Frequency vs. Temperature 1290 1260 5.5 V 1230 5.0 V FRC (kHz) 1200 4.5 V 4.0 V 3.3 V 2.7 V 1170 1140 1110 1080 1.8 V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-534.ATmega6490A: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 3.3 V 2.7 V 8.2 8.1 8 FRC (MHz) 7.9 1.8 V 7.8 7.7 7.6 7.5 7.4 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-535.ATmega6490A: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C 8 FRC (MHz) 7.9 -45 °C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-536.ATmega6490A: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.12 Current Consumption of Peripheral Units Figure 30-537.ATmega6490A: Brownout Detector Current vs. VCC 42 39 36 ICC (uA) 33 30 27 85 °C 25 °C -45 °C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-538.ATmega6490A: Active Supply Current with ADC at 50kHz vs. VCC 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-539.ATmega6490A: Active Supply Current with ADC at 200kHz vs. VCC 360 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-540.ATmega6490A: Active Supply Current with ADC at 1MHz vs. VCC 340 85 °C 25 °C -45 °C 310 ICC (uA) 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-541.ATmega6490A: AREF External Reference Current vs. VCC 170 85 °C 25 °C -45 °C 155 140 ICC (uA) 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-542.ATmega6490A: Watchdog Timer Current vs. VCC 18 85 °C 25 °C -45 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-543.ATmega6490A: Analog Comparator Current vs. VCC 110 25 °C 100 85 °C 90 ICC (uA) 80 -45 °C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-544.ATmega6490A: Programming Current vs. VCC 20 -45 °C 18 16 ICC (mA) 14 25 °C 12 10 85 °C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.9.13 Current Consumption in Reset and Reset Pulswidth Figure 30-545.ATmega6490A: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up ICC (mA) 0.16 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-546.ATmega6490A: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-547.ATmega6490A: Minimum Reset Pulse Width vs. VCC 2400 2100 Pulsewidth (ns) 1800 1500 1200 900 600 85 °C 25 °C -45 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10 ATmega6490P 30.10.1 Active Supply Current Figure 30-548.ATmega6490P: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.2 5.5 V 5.0 V 1 4.5 V ICC (mA) 0.8 4.0 V 0.6 3.3 V 2.7 V 0.4 1.8 V 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-549.ATmega6490P: Active Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-550.ATmega6490P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 7 85 °C 25 °C -45 °C 6 ICC (mA) 5 4 3 2 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-551.ATmega6490P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.45 25 °C 85 °C -45 °C 0.4 ICC (mA) 0.35 0.3 0.25 0.2 0.15 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-552.ATmega6490P: Active Supply Current vs. VCC (32kHz Watch Crystal) 85 °C 25 °C -45 °C 40 36 32 ICC (mA) 28 24 20 16 12 8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.10.2 Idle Supply Current Figure 30-553.ATmega6490P: Idle Supply Current vs.Low Frequency (0.1 - 1.0MHz) 0.3 5.5 V 0.27 5.0 V 4.5 V 0.24 ICC (mA) 0.21 0.18 4.0 V 0.15 3.3 V 0.12 2.7 V 0.09 1.8 V 0.06 0.03 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-554.ATmega6490P: Idle Supply Current vs. Frequency (1 - 20MHz) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 4.0 V 6 3.3 V 4 2.7 V 2 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 30-555.ATmega6490P: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 2 85 °C 25 °C -45 °C 1.8 1.6 ICC (mA) 1.4 1.2 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-556.ATmega6490P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.4 85 °C 25 °C -45 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-557.ATmega6490P: Idle Supply Current vs. VCC (32kHz Watch Crystal) 9.5 85 °C 8.5 25 °C -45 °C 7.5 ICC (mA) 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.10.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P are controlled by the Power Reduction Register. See ”PRR – Power Reduction Register” on page 46 for details. Table 30-19. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 23.75µA 212.1µA 938µA PRUSART0 36.7µA 210.4µA 939µA PRSPI 32.1µA 213µA 940µA PRTIM1 24.2µA 217µA 940µA PRLCD 27.3µA 208.8µA 935µA Table 30-20.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.4 Power-down Supply Current Figure 30-558.ATmega6490P: Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2.4 85 °C 2.2 2 1.8 ICC (uA) 1.6 1.4 1.2 1 0.8 25 °C -45 °C 0.6 0.4 0.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-559.ATmega6490P: Power-down Supply Current vs. VCC (Watchdog Timer Enabled 20 85 °C 25 °C -45 °C 18 16 ICC (uA) 14 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-560.ATmega649A: Power-down Supply Current vs. VCC (32kHz Watch Crystal) 1.5 85 °C 1.3 ICC (mA) 1.1 0.9 0.7 0.5 0.3 25 °C -45 °C 0.1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 30.10.5 Power-save Supply Current Figure 30-561.ATmega6490P: Power-save Supply Current vs. VCC (Watchdog Timer Disabled and 32kHz Crystal Oscillator Running) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.6 Standby Supply Current Figure 30-562.ATmega649A Standby Supply Current vs. VCC (32kHz Watch Crystal, Watchdog Timer Disabled) 2.5 85 °C 2.3 2.1 ICC (mA) 1.9 1.7 1.5 1.3 1.1 25 °C 0.9 -45 °C 0.7 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-563.ATmega6490P: Standby Supply Current vs. VCC (Xtall and Resonator, Watchdog Timer Disabled) 0.125 6MHz_res 6MHz_xtal 0.115 0.105 4MHz_xtal 4MHz_res 0.095 ICC (mA) 0.085 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.7 Pin Pull-up Figure 30-564.ATmega6490P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 140 120 IOP (uA) 100 80 60 40 25 °C 85 °C -45 °C 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) Figure 30-565.ATmega6490P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 10 25 °C 0 85 °C -45 °C 0 0.5 1 1.5 2 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-566.ATmega6490P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 50 45 40 IOP (uA) 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 25 °C 85 °C 1.8 -45 °C VOP (V) Figure 30-567.ATmega649A: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 105 IRESET (uA) 90 75 60 45 30 25 °C -45 °C 85 °C 15 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-568.ATmega6490P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 54 48 IRESET (uA) 42 36 30 24 18 12 25 °C -45 °C 85 °C 6 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 VRESET (V) Figure 30-569.ATmega6490P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 IRESET (uA) 30 25 20 15 10 25 °C -45 °C 85 °C 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.8 Pin Driver Strength Figure 30-570.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC=5V) 5 4.95 4.9 VOH (V) 4.85 4.8 4.75 -45 °C 4.7 4.65 25 °C 4.6 85 °C 4.55 0 1 2 3 4 5 6 7 8 9 10 IOH (mA) Figure 30-571.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC=2.7V) 2.7 2.6 2.5 VOH (V) 2.4 2.3 -45 °C 2.2 2.1 25 °C 2 85 °C 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-572.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Ports A, C, D, E, F, G (VCC=1.8V) 1.8 1.7 VOH (V) 1.6 1.5 -45 °C 1.4 25 °C 1.3 85 °C 1.2 0 0.5 1 1.5 2 2.5 3 3.5 4 IOH (mA) Figure 30-573.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Port B (VCC= 5V) 5 4.9 VOH (V) 4.8 4.7 4.6 -45 °C 4.5 25 °C 85 °C 4.4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-574.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 2.7V) 2.8 2.6 2.4 VOH (V) 2.2 2 -45 °C 1.8 25 °C 1.6 1.4 85 °C 1.2 0 2 4 6 8 10 12 14 16 18 20 IOH (mA) Figure 30-575.ATmega6490P: I/O Pin Output Voltage vs. Source Current, Port B (VCC = 1.8V) 1.8 1.75 1.7 VOH (V) 1.65 1.6 1.55 1.5 -45 °C 1.45 1.4 25 °C 85 °C 1.35 1.3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-576.ATmega6490P: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 5V) 0.6 85 °C 0.5 25 °C 0.4 VOL (V) -45 °C 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) Figure 30-577.ATmega6490P. I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 2.7V) 1.2 85 °C VOL (V) 1 0.8 25 °C 0.6 -45 °C 0.4 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-578.ATmega6490P: I/O Pin Output Voltage vs. Sink Current, Ports A, C, D, E, F, G (VCC = 1.8V) 0.32 85 °C 25 °C 0.28 0.24 -45 °C VOL (V) 0.2 0.16 0.12 0.08 0.04 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOL (mA) Figure 30-579.ATmega6490P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 5V) 0.6 85 °C 25 °C 0.5 -45 °C VOL (V) 0.4 0.3 0.2 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-580.ATmega6490P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 2.7V) 1.2 85 °C 1 25 °C VOL (V) 0.8 -45 °C 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) Figure 30-581.ATmega6490P: I/O Pin Output Voltage vs. Sink Current, Port B (VCC = 1.8V) 0.5 85 °C 0.45 25 °C 0.4 0.35 -45 °C VOL (V) 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.9 Pin Threshold and Hysteresis Figure 30-582.ATmega6490P: I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3.1 85 °C 25 °C -45 °C 2.9 2.7 Threshold (V) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-583.ATmega6490P: I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0” 2.4 85 °C 25 °C -45 °C 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 1.5 2 2.5 3 3.5 4 4.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-584.ATmega6490P: I/O Pin Input Hysteresis vs. VCC 0.6 -45 °C 0.55 Input Hysteresis (V) -45 °C 0.5 25 °C 0.45 0.4 85 °C 0.35 0.3 0.25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-585.ATmega6490P: Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) -45 °C 25 °C 85 °C 2.4 2.2 Threshold (V) 2 1.8 1.6 1.4 1.2 1 0.8 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-586.ATmega6490P: Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 85 °C 25 °C -45 °C 2.4 2.2 2 Threshold (V) 1.8 1.6 1.4 1.2 1 0.8 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-587.ATmega6490P: Reset Input Pin Hysteresis vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -45 °C 25 °C 85 °C 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.10 BOD Thresholds and Analog Comparator Offset Figure 30-588.ATmega6490P: BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.41 Rising Vcc BOD threshold (V) 4.39 4.37 4.35 Falling Vcc 4.33 4.31 4.29 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-589.ATmega6490P: BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.795 2.785 Rising Vcc 2.775 BOD threshold (V) 2.765 2.755 2.745 2.735 Falling Vcc 2.725 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-590.ATmega6490P: BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.845 Rising Vcc 1.84 BOD threshold (V) 1.835 1.83 1.825 Falling Vcc 1.82 1.815 1.81 1.805 1.8 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-591.ATmega6490P: Bandgap Voltage vs. VCC 1.103 1.101 Bandgap Voltage (V) 1.099 25 °C 1.097 85 °C 1.095 1.093 1.091 1.089 1.087 1.085 -45 °C 1.083 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-592.ATmega6490P: Bandgap Voltage vs. Temperature 1.11 1.8 V 1.108 3.3 V Bandgap Voltage (V) 1.106 5.0 V 1.104 5.5 V 1.102 1.1 1.098 1.096 1.094 1.092 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) 30.10.11 Internal Oscillator Speed Figure 30-593.ATmega6490P: Watchdog Oscillator Frequency vs. VCC 1290 -45 °C 25 °C 1260 85 °C 1230 FRC (kHz) 1200 1170 1140 1110 1080 1050 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-594.ATmega6490P: Watchdog Oscillator Frequency vs. Temperature 1290 1260 5.5 V 1230 5.0 V FRC (kHz) 1200 4.5 V 4.0 V 3.3 V 2.7 V 1170 1140 1110 1080 1.8 V 1050 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature (°C) Figure 30-595.ATmega6490P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature 5.5 V 4.0 V 3.3 V 2.7 V 8.2 8.1 8 FRC (MHz) 7.9 1.8 V 7.8 7.7 7.6 7.5 7.4 7.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-596.ATmega6490P: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.2 85 °C 8.1 25 °C 8 FRC (MHz) 7.9 -45 °C 7.8 7.7 7.6 7.5 7.4 7.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-597.ATmega6490P: Calibrated 8MHz RC Oscillator Frequency vs.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.12 Current Consumption of Peripheral Units Figure 30-598.ATmega6490P: Brownout Detector Current vs. VCC 42 39 36 ICC (uA) 33 30 27 85 °C 25 °C -45 °C 24 21 18 15 12 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-599.ATmega6490P: Active Supply Current with ADC at 50kHz vs. VCC 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-600.ATmega6490P: Active Supply Current with ADC at 200kHz vs. VCC 360 85 °C 25 °C -45 °C 330 300 ICC (uA) 270 240 210 180 150 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-601.ATmega6490P: Active Supply Current with ADC at 1MHz vs. VCC 340 85 °C 25 °C -45 °C 310 ICC (uA) 280 250 220 190 160 130 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-602.ATmega6490P: AREF External Reference Current vs. VCC 170 85 °C 25 °C -45 °C 155 140 ICC (uA) 125 110 95 80 65 50 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-603.ATmega6490P: Watchdog Timer Current vs. VCC 18 85 °C 25 °C -45 °C 16 14 ICC (uA) 12 10 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-604.ATmega6490P: Analog Comparator Current vs. VCC 110 25 °C 100 85 °C 90 ICC (uA) 80 -45 °C 70 60 50 40 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 30-605.ATmega6490P: Programming Current vs. VCC 20 -45 °C 18 16 ICC (mA) 14 25 °C 12 10 85 °C 8 6 4 2 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 30.10.13 Current Consumption in Reset and Reset Pulswidth Figure 30-606.ATmega6490P: Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up ICC (mA) 0.16 0.14 5.5 V 0.12 5.0 V 0.1 4.5 V 4.0 V 0.08 3.3 V 0.06 2.7 V 0.04 1.8 V 0.02 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 30-607.ATmega6490P: Reset Supply Current vs. VCC (1 - 20MHz, Excluding Current Through The Reset Pull-up) 2.4 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Figure 30-608.ATmega6490P: Minimum Reset Pulse Width vs. VCC 2400 2100 Pulsewidth (ns) 1800 1500 1200 900 600 85 °C 25 °C -45 °C 300 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 31. Register Summary Note: Address Name Registers with bold type only available in ATmega3290A/3290PA/6490A/6490P.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Address Name (0xC4) UBRR0L (0xC3) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - USART0 Baud Rate Register Low - - - - - Page 203 (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 201 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 200 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 199 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - -
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x85) TCNT1H Timer/Counter1 High (0x84) TCNT1L Timer/Counter1 Low (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 136 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 135 133 - - 137 137 - - - (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 218 (0x7E) DIDR0 ADC7
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - COM0A0 WGM01 CS02 CS01 CS00 142 - - - PSR2 PSR10 146/165 - - 0x26 (0x46) TCNT0 Timer/Counter0 0x25 (0x45) Reserved - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 0x23 (0x43) GTCCR TSM - - 0x22 (0x42) EEARH - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - Page 144 EER
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 32.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 L
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33. Ordering Information 33.1 ATmega169A Speed (MHz)(3) 16 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATmega169A-AU ATmega169A-AUR(4) ATmega169A-MU ATmega169A-MUR(4) ATmega169A-MCH ATmega169A-MCHR(4) Package Type(1) 64A 64A 64M1 64M1 64MC 64MC Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.2 ATmega169PA Speed (MHz)(3) 16 Notes: Power Supply Ordering Code(2) Package Type(1) 64A 64A 64M1 64M1 64MC 64MC Industrial (-40°C to 85°C) 1.8 - 5.5V ATmega169PA-AU ATmega169PA-AUR(4) ATmega169PA-MU ATmega169PA-MUR(4) ATmega169PA-MCH ATmega169PA-MCHR(4) ATmega169PA-AN ATmega169PA-ANR(4) ATmega169PA-MN ATmega169PA-MNR(4) 64A 64A 64M1 64M1 Extended (-40°C to 105°C)(5) Operational Range 1. This device can also be supplied in wafer form.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.3 ATmega329A Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATmega329A-AU ATmega329A-AUR(4) ATmega329A-MU ATmega329A-MUR(4) Package Type(1) 64A 64A 64M1 64M1 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.4 ATmega329PA Speed (MHz)(3) 20 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATmega329PA-AU ATmega329PA-AUR(4) ATmega329PA-MU ATmega329PA-MUR(4) Package Type(1) 64A 64A 64M1 64M1 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.5 ATmega3290A Speed (MHz)(3) Power Supply 20 1.8 - 5.5V Notes: Ordering Code(2) ATmega3290A-AU ATmega3290A-AUR(4) Package Type(1) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.6 ATmega3290PA Speed (MHz)(3) Power Supply 20 1.8 - 5.5V Notes: Ordering Code(2) ATmega3290PA-AU ATmega3290PA-AUR(4) Package Type(1) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.7 ATmega649A Speed (MHz)(3) 16 Notes: Power Supply 1.8 - 5.5V Ordering Code(2) ATmega649A-AU ATmega649A-AUR(4) ATmega649A-MU ATmega649A-MUR(4) Package Type(1) 64A 64A 64M1 64M1 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.8 ATmega649P Speed (MHz)(3) 16 Notes: Power Supply 1.8 - 5.5 V Ordering Code(2) ATmega649P-AU ATmega649P-AUR(4) ATmega649P-MU ATmega649P-MUR(4) Package Type(1) 64A 64A 64M1 64M1 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.9 ATmega6490A Speed (MHz)(3) Power Supply 20 1.8 - 5.5V Notes: Ordering Code(2) ATmega6490A-AU ATmega6490A-AUR(4) Package Type(1) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 33.10 ATmega6490P Speed (MHz)(3) Power Supply 20 1.8 - 5.5V Notes: Ordering Code(2) ATmega6490P-AU ATmega6490P-AUR(4) Package Type(1) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 34. Packaging Information 34.1 64A PIN 1 B PIN 1 e B PIN 1 IDENTIFIER e PIN 1 IDENTIFIER E1 E E1 E D1 D1 DD C C 0°~7° 0°~7° A1 A1 A2 A2 AA LL COMMON DIMENSIONS COMMON DIMENSIONS (Unit of of Measure = mm) (Unit Measure = mm) SYMBOL MIN SYMBOL MIN – – – A1 0.05 – A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 E 15.75 16.00 16.25 A A1 A2 D D1 Notes: E Notes: 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 34.2 64M1 D D Marked Pin# 1 ID Marked Pin# 1 ID E E SEATING PLANE CSEATING PLANE C A1 A1 TOP VIEW TOP VIEW AA KK 0.08 C C 0.08 L L Pin Pin #1 #1 Corner Corner D2 D2 11 22 33 Option A Option SIDEVIEW VIEW SIDE Pin Pin#1 #1 Triangle Triangle COMMON DIMENSIONS COMMON DIMENSIONS (Unit of of Measure = mm) (Unit Measure = mm) SYMBOL MIN SYMBOL MIN E2E2 Option B Option B Pin #1 Pin #1 Chamfer Chamfer (C 0.30) (C 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 34.3 64MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT eT/2 L eR A26 A34 B23 B30 COMMON DIMENSIONS (Unit of Measure = mm) A1 A25 B1 B22 R0.20 0.40 b D2 SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.28 C eT B7 B16 A8 A18 A9 A17 L (0.18) REF B8 B15 E2 K BOTTOM VIEW Note: 1. The terminal #1 ID is a Laser-marked Feature. Package Drawing Contact: packagedrawings@atmel.com (0.1) REF NOTE 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 34.4 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. MIN NOM MAX A – – 1.20 A1 0.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 35. Errata 35.1 ATmega169A No known errata 35.2 ATmega169A/169PA Rev. A to F Not sampled. 35.3 ATmega169PA Rev. G No known errata. 35.4 ATmega329A/329PA rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer • Using BOD disable will make the chip reset 1.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 35.6 ATmega329A/329PA rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 35.9 ATmega3290A/3290PA rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 36. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 36.1 Rev. 8284D - 06/11 1. 2. 36.2 Rev. 8284C - 06/11 1. 2. 36.3 Updated ”Signature Bytes” on page 313. A, P, and PA devices have different signature (0x002) bytes. Updated all ”DC Characteristics” on page 344. Rev. 8284B - 03/11 1. 2. 3. 36.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Pinout - 64A (TQFP) and 64M1 (QFN/MLF) ..............................................................2 1.2Pinout - 100A (TQFP) ................................................................................................
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 9.2Clock Sources .........................................................................................................31 9.3Default Clock Source ...............................................................................................31 9.4Calibrated Internal RC Oscillator .............................................................................32 9.5Crystal Oscillator ................................................................................
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 13.3Register Description ..............................................................................................62 14 I/O-Ports .................................................................................................. 66 14.1Overview ...............................................................................................................66 14.2Ports as General Digital I/O ....................................................................
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 18.1Features ..............................................................................................................147 18.2Overview .............................................................................................................147 18.3Timer/Counter Clock Sources .............................................................................148 18.4Counter Unit ...................................................................................
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 22.1Overview .............................................................................................................216 22.2Analog Comparator Multiplexed Input .................................................................216 22.3Register Description ............................................................................................217 23 Analog to Digital Converter ................................................................ 219 23.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 26.5Boundary-scan Chain ..........................................................................................264 26.6ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P Boundary-scan Order 273 26.7Boundary-scan Description Language Files ........................................................292 26.8Register Description ............................................................................................
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 29.10ADC Characteristics ..........................................................................................357 29.11LCD Controller Characteristics ..........................................................................358 30 Typical Characteristics ........................................................................ 359 30.1ATmega169A ......................................................................................................359 30.
ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P 35.3ATmega169PA Rev. G ........................................................................................700 35.4ATmega329A/329PA rev. A ................................................................................700 35.5ATmega329A/329PA rev. B ................................................................................700 35.6ATmega329A/329PA rev. C ................................................................................701 35.
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