Datasheet

51
8021G–AVR–03/11
ATmega329P/3290P
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit
has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written
to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm
described above. ”Timed Sequences for Changing the Configuration of the Watchdog Timer” on
page 49.
• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Time-out Periods
are shown in Table 10-2 on page 51.
Table 10-2. Watchdog Timer Prescale Select
WDP2 WDP1 WDP0
Number of WDT
Oscillator Cycles
Typical Time-out at
V
CC
= 3.0V
Typical Time-out at
V
CC
= 5.0V
0 0 0 16K cycles 17.1ms 16.3ms
0 0 1 32K cycles 34.3ms 32.5ms
0 1 0 64K cycles 68.5ms 65ms
0 1 1 128K cycles 0.14s 0.13s
1 0 0 256K cycles 0.27s 0.26s
1 0 1 512K cycles 0.55s 0.52
1 1 0 1,024K cycles 1.1s 1.0s
1 1 1 2,048K cycles 2.2s 2.1s