Datasheet

42
8021G–AVR–03/11
ATmega329P/3290P
9.11 Register Description
9.11.1 SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 9-2.
Note: 1. Standby mode is only recommended for use with external crystals or resonators.
• Bit 1 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
9.11.2 MCUCR – MCU Control Register
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1
on page 37. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
Bit 76543210
0x33 (0x53)
– – – – SM2 SM1 SM0 SE SMCR
Read/Write RRRRR/WR/WR/WR/W
Initial Value00000000
Table 9-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
000Idle
0 0 1 ADC Noise Reduction
010Power-down
011Power-save
100Reserved
101Reserved
110Standby
(1)
111Reserved
Bit 7 6 5 4 3 2 1 0
0x35 (0x55)
JTD BODS BODSE PUD – – IVSEL IVCE MCUCR
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0