Datasheet

311
8021G–AVR–03/11
ATmega329P/3290P
Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 27-7 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to load-
ing operation.
Figure 27-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 27-7 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to read-
ing operation.Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET
is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET
is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 27-16 on page 312, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ