Datasheet

259
8021G–AVR–03/11
ATmega329P/3290P
Figure 25-3. General Port Pin Schematic Diagram
25.5.2 Scanning the RESET Pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 25-4 is
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 25-4. Observe-only Cell
CLK
RPx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
WPx: WRITE PINx REGISTER
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
Q
Q
D
Q
Q
D
CLR
DDxn
PINxn
DATA B U S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
Description for Details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
RPx: READ PORTx PIN
RRx
RESET
Q
Q
D
CLR
PORTxn
WPx
0
1
WRx
0
1
DQ
From
Previous
Cell
ClockDR
ShiftDR
To
Next
Cell
From System Pin
To System Logic
FF1