Datasheet

245
8021G–AVR–03/11
ATmega329P/3290P
is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation
is shown in Table 23-6 on page 245.
23.5.4 LCDCCR – LCD Contrast Control Register
• Bits 7:5 – LCDDC2:0: LDC Display Configuration
The LCDDC2:0 bits determine the amount of time the LCD drivers are turned on for each volt-
age transition on segment and common pins. A short drive time will lead to lower power
consumption, but displays with high internal resistance may need longer drive time to achieve
satisfactory contrast. Note that the drive time will never be longer than one half prescaled LCD
clock period, even if the selected drive time is longer. When using static duty or blanking, drive
time will always be one half prescaled LCD clock period.
New values take effect immediately, and can cause small glitches in the display output. This can
be avoided by setting the LCDBL in LCDCRA, and wait to the next start of frame before chang-
ing LCDDC2:0.
Note: The drive time will be longer dependent on oscillator startup time.
• Bit 4 – LCDMDT: LCD Maximum Drive Time
Writing this bit to one turns the LCD drivers on 100% all the time, regardless of the drive time
configured by LCDDC2:0.
Table 23-6. Example of frame rate calculation
clk
LCD
duty K N LCDCD2:0 D Frame Rate
4MHz 1/4 8 2048 011 4 4000000/(8*2048*4) = 61Hz
4MHz 1/3 6 2048 011 4 4000000/(6*2048*4) = 81Hz
32.768kHz Static 8 16 000 1 32768/(8*16*1) = 256Hz
32.768kHz 1/2 8 16 100 5 32768/(8*16*5) = 51Hz
Bit 76543210
(0xE7)
LCDDC2 LCDDC1 LCDDC0 LCDNDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 LCDCCR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 23-7. LCD Display Configuration
LCDDC2 LCDDC1 LCDDC0 Nominal drive time
0 0 0 300µs
00170µs
0 1 0 150µs
0 1 1 450µs
1 0 0 575µs
1 0 1 850µs
1 1 0 1150µs
1 1 1 50% of clk
LCD_PS