Datasheet

228
8021G–AVR–03/11
ATmega329P/3290P
22.9.3 ADCL and ADCH – The ADC Data Register
22.9.3.1 ADLAR = 0
22.9.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. When ADCL is
read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on
page 223.
22.9.4 ADCSRB – ADC Control and Status Register B
101 32
110 64
111 128
Table 22-5. ADC Prescaler Selections (Continued)
ADPS2 ADPS1 ADPS0 Division Factor
Bit 151413121110 9 8
(0x79) – – – – – – ADC9 ADC8 ADCH
(0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 151413121110 9 8
(0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
(0x78) ADC1 ADC0 – – – – – – ADCL
76543210
Read/Write RRRRRRRR
RRRRRRRR
Initial Value 0 0 0 0 0 0 0 0
00000000
Bit 76543210
(0x7B) –
ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0