Datasheet

22
8021G–AVR–03/11
ATmega329P/3290P
7.6 Register Description
7.6.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 7-1. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section “7.4.2” on page 20. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
7.6.2 EEARH and EEARL – EEPROM Address Register ATmega329P/3290P
• Bits 15:10 – Reserved
These bits are reserved and will always read as zero.
• Bits 9:0 – EEAR[9:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 1023.
The initial value of EEAR is undefined. A proper value must be written before the EEPROM may
be accessed.
7.6.3 EEDR – EEPROM Data Register
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
Bit 151413121110 9 8
0x22 (0x42) ––––––EEAR9EEAR8EEARH
0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543210
Read/WriteRRRRRR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 X X X
XXXXXXXX
Bit 76543210
0x20 (0x40) MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0