Datasheet

213
8021G–AVR–03/11
ATmega329P/3290P
When this bit is wr itten logic one, the di gital input buffer on the AIN1/0 pin is disabled. The cor respondin g PIN Register bit will always read a s zero when this bit is set. When an analog si gnal is applied to the AIN1/0 pin and the digi tal input from t his pin i s not neede d, this bit s hould be written logic one to reduce pow er consump tion in the digital input buffer.
22. Analog to Digital Converter
22.1 Features
• 10-bit Resolution
• 0.5LSB Integral Non-linearity
• ± 2LSB Absolute Accuracy
• 13 - 260µs Conversion Time (50kHz to 1MHz ADC clock)
• Up to 76.9kSPS at Maximum Resolution (200kHz ADC clock)
• Eight Multiplexed Single Ended Input Channels
• Optional Left Adjustment for ADC Result Readout
• 0 - V
CC
ADC Input Voltage Range
• Selectable 1.1V ADC Reference Voltage
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
22.2 Overview
The ATmega329P/3290P features a 10-bit successive approximation ADC. The ADC is con-
nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs
constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 22-1.
The ADC has a separate analog supply voltage pin, AVCC. AV
CC
must not differ more than ±
0.3V from V
CC
. See the paragraph ”ADC Noise Canceler” on page 219 on how to connect this
pin.
Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-
ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.
The PRADC, in ”PRR – Power Reduction Register” on page 43 must be written to zero to enable
the ADC module.