Datasheet

8021G–AVR–03/11

ATmega329P/3290P

18. SPI – Serial Peripheral Interface

18.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

18.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega329P/3290P and peripheral devices or between several AVR devices. A simplified block

diagram of the Serial Peripheral Interface is shown in Figure 18-1.

The PRSPI bit in ”Power Reduction Register” on page 39 must be written to zero to enable the

SPI module.

Figure 18-1. SPI Block Diagram

(1)

Note: 1. Refer to Figure 1-2 on page 3, and Table 13-6 on page 72 for SPI pin placement.

SPI2X

DIVIDER

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