Datasheet

156
8021G–AVR–03/11
ATmega329P/3290P
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM21:0 bit setting. Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits
are set to a normal or CTC mode (non-PWM).
Table 17-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on
page 147 for more details.
Table 17-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
rect PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See ”Phase Correct PWM Mode” on
page 149 for more details.
• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
17-6 on page 157.
Table 17-3. Compare Output Mode, non-PWM Mode
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
0 1 Toggle OC2A on compare match.
1 0 Clear OC2A on compare match.
1 1 Set OC2A on compare match.
Table 17-4. Compare Output Mode, Fast PWM Mode
(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01Reserved
10
Clear OC2A on compare match, set OC2A at BOTTOM
(non-inverting mode)
11
Set OC2A on compare match, clear OC2A at BOTTOM
(inverting mode).
Table 17-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected.
01Reserved
10
Clear OC2A on compare match when up-counting. Set OC2A on
compare match when counting down.
11
Set OC2A on compare match when up-counting. Clear OC2A on
compare match when counting down.