Datasheet

141
8021G–AVR–03/11
ATmega329P/3290P
17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
17.1 Features
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A)
• Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
17.2 Overview
Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-
fied block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement
of I/O pins, refer to ”MLF/ Pinout ATmega329P” on page 2 and ”TQFP / Pinout ATmega3290P”
on page 3. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the ”Register Description” on page
155.
Figure 17-1. 8-bit Timer/Counter Block Diagram
17.2.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter-
rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
Timer/Counter
DATA B U S
=
TCNTn
Waveform
Generation
OCnx
= 0
Control Logic
= 0xFF
TOPBOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCnx
(Int.Req.)
Synchronization Unit
OCRnx
TCCRnx
ASSRn
Status flags
clk
I/O
clk
ASY
Synchronized Status flags
asynchronous mode
select (ASn)
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
Tn
clk
I/O