Features • • • • • • • • • • High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20MIPS Throughput at 20MHz (ATmega329P/3290P) – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega329P/ATmega3290P) – EEPROM • 1Kbytes (ATmega329P/ATmega3290P)
ATmega329P/3290P 1. Pin Configurations LCDCAP 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (COM0) PA1 (COM1) PA2 (COM2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 MLF/ Pinout ATmega329P 64 Figure 1-1.
ATmega329P/3290P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 DNC GND VCC DNC PA0 (COM0) PA1 (COM1) PA2 (COM2) 80 79 78 77 76 DNC 88 81 DNC 89 82 PF7 (ADC7/TDI) 90 DNC PF6 (ADC6/TDO) 91 83 PF5 (ADC5/TMS) 92 PH5 (PCINT21/SEG38) PF4 (ADC4/TCK) 93 PH4 (PCINT20/SEG39) PF3 (ADC3) 94 84 PF2 (ADC2) 95 85 PF1 (ADC1) 96 PH7 (PCINT23/SEG36) PF0 (ADC0) PH6 (PCINT22/SEG37) AREF 97 86 AGND 98 87 AVCC 99 TQFP / Pinout ATmega3290P 1
ATmega329P/3290P 2. Overview The ATmega329P/3290P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329P/3290P achieves throughputs approaching 1MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram GND Block Diagram PF0 - PF7 VCC PORTA DRIVERS PORTF DRIVERS DATA DIR. REG.
ATmega329P/3290P resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega329P/3290P 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7...PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
ATmega329P/3290P 2.3.7 Port E (PE7...PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega329P/3290P 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset Characteristics” on page 336. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.
ATmega329P/3290P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
ATmega329P/3290P 6. AVR CPU Core 6.1 Overview This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1.
ATmega329P/3290P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
ATmega329P/3290P specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 6.4.
ATmega329P/3290P 6.5 General Purpose Register File The Register File is optimized for the Atmel®AVR® Enhanced RISC instruction set.
ATmega329P/3290P 6.5.1 The X-register, Y-register, and Z-register The registers R26...R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3. Figure 6-3.
ATmega329P/3290P 6.6.1 SPH and SPL – Stack pointer High and Stack Pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 6.
ATmega329P/3290P Figure 6-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 6.8 Reset and Interrupt Handling The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space.
ATmega329P/3290P Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
ATmega329P/3290P 7. AVR Memories 7.1 Overview This section describes the different memories in the ATmega329P/3290P. The Atmel®AVR® architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega329P/3290P features an EEPROM Memory for data storage. All three memory spaces are linear. 7.2 In-System Reprogrammable Flash Program Memory The ATmega329P/3290P contains 132Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
ATmega329P/3290P The Atmel®AVR® ATmega329P/3290P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower 2304 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM.
ATmega329P/3290P Figure 7-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 7.4 Next Instruction EEPROM Data Memory The ATmega329P/3290P contains 1Kbytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
ATmega329P/3290P be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 7.5 I/O Memory The I/O space definition of the ATmega329P/3290P is shown in ”Register Summary” on page 403. All ATmega329P/3290P I/Os and peripherals are placed in the I/O space.
ATmega329P/3290P 7.6 7.6.1 Register Description EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 7-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down.
ATmega329P/3290P 7.6.4 EECR – EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 EECR • Bits 7:4 – Reserved These bits are reserved bits and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt.
ATmega329P/3290P • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.
ATmega329P/3290P Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega329P/3290P Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega329P/3290P 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the Atmel®AVR® and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 37. The clock systems are detailed below. Figure 8-1.
ATmega329P/3290P 8.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. It also allows the LCD controller output to continue while the rest of the device is in sleep mode. 8.1.
ATmega329P/3290P 8.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATmega329P/3290P Table 8-4. CKSEL0 Start-up Time from Power-down and Power-save SUT1..0 (2) Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 11 1K CK 14CK + 4.1ms Ceramic resonator, fast rising power 1 00 1K CK(2) 14CK + 65ms Ceramic resonator, slowly rising power 01 16K CK 14CK Crystal Oscillator, BOD enabled 10 16K CK 14CK + 4.1ms Crystal Oscillator, fast rising power 11 16K CK 14CK + 65ms Crystal Oscillator, slowly rising power 1 1 1 Notes: 8.
ATmega329P/3290P The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using: Ce + Ci = 2 ⋅ CL – C s where Ce - is optional external capacitors as described in Figure 8-2 on page 29 Ci - is the pin capacitance in Table 8-7 on page 31 CL - is the load capacitance for a 32.768kHz crystal specified by the crystal vendor. CS - is the total stray capacitance for one TOSC pin.
ATmega329P/3290P When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section ”Calibration Byte” on page 299. Table 8-9. Notes: Internal Calibrated RC Oscillator Operating Modes(1)(3) Frequency Range(2) (MHz) CKSEL3...0 7.3 - 8.1 0010 1. The device is shipped with this option selected. 2. The frequency ranges are preliminary values. 3.
ATmega329P/3290P Table 8-12. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.1ms Fast rising power 10 6 CK 14CK + 65ms Slowly rising power 11 Recommended Usage BOD enabled Reserved When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU.
ATmega329P/3290P 8.10.1 Switching Time When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occur in the clock system and that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU’s clock frequency.
ATmega329P/3290P 8.11 8.11.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega329P/3290P 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”.
ATmega329P/3290P 9. Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
ATmega329P/3290P 9.3 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 27-3 on page 297, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page 37. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
ATmega329P/3290P USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.
ATmega329P/3290P mode and active mode to reduce the overall power consumption. In all other sleep modes, the clock is already stopped. 9.10 Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled.
ATmega329P/3290P 9.10.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled.
ATmega329P/3290P 9.11 9.11.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2. Table 9-2.
ATmega329P/3290P • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 9.11.3 PRR – Power Reduction Register Bit 7 6 5 4 3 2 1 0 (0x64) – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bits 7:5 – Reserved These bits are reserved and will always read as zero.
ATmega329P/3290P 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega329P/3290P Figure 10-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 336.
ATmega329P/3290P Figure 10-2. MCU Start-up, RESET Tied to VCC VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 10-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics” on page 336) will generate a reset, even if the clock is not running.
ATmega329P/3290P 10.2.3 Brown-out Detection ATmega329P/3290P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
ATmega329P/3290P 10.3 Internal Voltage Reference ATmega329P/3290P features an internal bandgap reference. This reference is used for Brownout Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”System and Reset Characteristics” on page 336. To save power, the reference is not always turned on.
ATmega329P/3290P Figure 10-7. Watchdog Timer WATCHDOG OSCILLATOR 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.4.2 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction.
ATmega329P/3290P 10.5 10.5.1 Register Description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) – – – JTRF WDRF BORF EXTRF PORF Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 MCUSR See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
ATmega329P/3290P • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2.
ATmega329P/3290P The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega329P/3290P 11. Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in Atmel ® AVR ® ATmega329P/3290P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 16. 11.2 Interrupt Vectors Table 11-1. Reset and Interrupt Vectors Vector No.
ATmega329P/3290P 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3290P. Table 11-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings.
ATmega329P/3290P 0x0034 ldi r16, low(RAMEND) 0x0035 out SPL,r16 0x0036 sei 0x0037 xxx ... ... ...
ATmega329P/3290P 0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 11.2.
ATmega329P/3290P Assembly Code Example Move_interrupts: ;Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
ATmega329P/3290P 12. External Interrupts 12.1 Overview The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins(2). Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles.
ATmega329P/3290P 12.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 12-1. Figure 12-1. Pin Change Interrupt pin_lat PCINT(0) D pcint_in_(0) Q 0 pcint_setflag pcint_syn PCIF pin_sync LE x clk PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 12.3 12.3.
ATmega329P/3290P Table 12-1. 12.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
ATmega329P/3290P 12.3.3 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 PCIF3(1) PCIF2(1) PCIF1 PCIF0 – – – INTF0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bit 7 – PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
ATmega329P/3290P 12.3.4 PCMSK3 – Pin Change Mask Register 3(1) Bit 7 6 5 4 3 2 1 0 (0x73) – PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK3 • Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30...24 Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATmega329P/3290P 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega329P/3290P Functions” on page 69. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2.
ATmega329P/3290P be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
ATmega329P/3290P Figure 13-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega329P/3290P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega329P/3290P 13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega329P/3290P 13.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 13-5.
ATmega329P/3290P Table 13-2. Signal Name Generic Description of Overriding Signals for Alternate Functions Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega329P/3290P 13.3.1 Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 13-3.
ATmega329P/3290P Table 13-5. 13.3.
ATmega329P/3290P • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt Source 14: The PB6 pin can serve as an external interrupt source.
ATmega329P/3290P low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source. Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 69.
ATmega329P/3290P 13.3.3 Alternate Functions of Port C The Port C has an alternate function as SEG for the LCD Controller. Table 13-9.
ATmega329P/3290P Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0 13.3.
ATmega329P/3290P Table 13-13 and Table 13-14 relates the alternate functions of Port D to the overriding signals shown in Figure 13-5 on page 69. Table 13-13.
ATmega329P/3290P 13.3.5 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Table 13-15.
ATmega329P/3290P • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
ATmega329P/3290P Table 13-17.
ATmega329P/3290P • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
ATmega329P/3290P Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 13.3.7 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-21.
ATmega329P/3290P • SEG – Port G, Bit 2 SEG, LCD front plane 4/4. • SEG – Port G, Bit 1 SEG, Segment driver 17/13. • SEG – Port G, Bit 0 SEG, LCD front plane 18/14. Table 13-21 and Table 13-22 relates the alternate functions of Port G to the overriding signals shown in Figure 13-5 on page 69. Table 13-22.
ATmega329P/3290P Table 13-23. Overriding Signals for Alternate Functions in PG3:0 13.3.
ATmega329P/3290P • PCINT22/SEG – Port H, Bit 6 PCINT22, Pin Change Interrupt Source 22: The PH6 pin can serve as an external interrupt source. SEG, LCD front plane 37. • PCINT21/SEG – Port H, Bit 5 PCINT21, Pin Change Interrupt Source 21: The PH5 pin can serve as an external interrupt source. SEG, LCD front plane 38. • PCINT20/SEG – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. SEG, LCD front plane 39.
ATmega329P/3290P Table 13-25 and Table 13-26 relates the alternate functions of Port H to the overriding signals shown in Figure 13-5 on page 69. Table 13-25.
ATmega329P/3290P 13.3.9 Alternate Functions of Port J Port J is only present in ATmega3290P. The alternate pin configuration is as follows: Table 13-27.
ATmega329P/3290P • PCINT28/SEG – Port J, Bit 4 PCINT28, Pin Change Interrupt Source 28: The PE28 pin can serve as an external interrupt source. SEG, LCD front plane 29. • PCINT27/SEG – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. SEG, LCD front plane 30. • PCINT26/SEG – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source. SEG, LCD front plane 31.
ATmega329P/3290P Table 13-29.
ATmega329P/3290P 13.4 13.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
ATmega329P/3290P 13.4.8 PORTC – Port C Data Register Bit 13.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.4.
ATmega329P/3290P 13.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 13.4.17 PORTF – Port F Data Register Bit 13.4.
ATmega329P/3290P 13.4.24 DDRH – Port H Data Direction Register(1) Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xD9) 13.4.25 PINH – Port H Input Pins Address(1) Bit 7 6 5 4 3 2 1 0 PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A (0xD8) 13.4.26 13.4.27 13.4.
ATmega329P/3290P 14. 8-bit Timer/Counter0 with PWM 14.1 Features • • • • • • • 14.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module.
ATmega329P/3290P The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output Compare Unit” on page 97 for details. The compare match event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 14.2.
ATmega329P/3290P clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
ATmega329P/3290P 14.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed.
ATmega329P/3290P 14.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled). 14.5.
ATmega329P/3290P Figure 14-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega329P/3290P 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
ATmega329P/3290P the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 14.7.
ATmega329P/3290P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 17-4 on page 156). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega329P/3290P Figure 14-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATmega329P/3290P symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 14.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
ATmega329P/3290P Figure 4 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 4.
ATmega329P/3290P 15. 16-bit Timer/Counter1 15.1 Features • • • • • • • • • • • 15.2 True 16-bit Design (i.e.
ATmega329P/3290P Figure 15-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 15.2.1 TCCRnB 1.
ATmega329P/3290P put Compare Units” on page 115. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
ATmega329P/3290P 15.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega329P/3290P the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega329P/3290P The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega329P/3290P 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega329P/3290P The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
ATmega329P/3290P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 109. 15.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
ATmega329P/3290P cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega329P/3290P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega329P/3290P 15.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
ATmega329P/3290P OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 127. For fast PWM mode refer to Table 15-3 on page 128, and for phase correct and phase and frequency correct PWM refer to Table 15-4 on page 128. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits.
ATmega329P/3290P Figure 15-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega329P/3290P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATmega329P/3290P to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega329P/3290P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: ( TOP + 1 ) R PCPWM = log ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ATmega329P/3290P ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output.
ATmega329P/3290P log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 15-9.
ATmega329P/3290P if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 1 on page 128).
ATmega329P/3290P Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega329P/3290P Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 15.11 Register Description 15.11.
ATmega329P/3290P Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 15-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega329P/3290P Waveform Generation Mode Bit Description(1) Table 15-5.
ATmega329P/3290P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
ATmega329P/3290P A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 15.11.
ATmega329P/3290P 15.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
ATmega329P/3290P 15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR1 • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ATmega329P/3290P 16. Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.0.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
ATmega329P/3290P Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle.
ATmega329P/3290P 16.1 16.1.1 Register Description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode.
ATmega329P/3290P Table 16-2. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on compare match 1 0 Clear OC0A on compare match 1 1 Set OC0A on compare match Table 16-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 16-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected.
ATmega329P/3290P • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 16-5. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
ATmega329P/3290P 16.1.4 TIMSK0 – Timer/Counter 0 Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – – OCIE0A TOIE0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled.
ATmega329P/3290P 16.1.6 GTCCR – General Timer/Counter Control Register Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted.
ATmega329P/3290P 17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 17.1 Features • • • • • • • 17.
ATmega329P/3290P (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value.
ATmega329P/3290P 17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surrounding environment. Figure 17-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
ATmega329P/3290P Generator for handling the special cases of the extreme values in some modes of operation. See ”Modes of Operation” on page 146. Figure 17-3 shows a block diagram of the Output Compare unit. Figure 17-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes.
ATmega329P/3290P 17.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation.
ATmega329P/3290P Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. See ”Register Description” on page 155. 17.6.
ATmega329P/3290P The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 17-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag.
ATmega329P/3290P for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 17-6.
ATmega329P/3290P A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.7.
ATmega329P/3290P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 17-5 on page 156). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega329P/3290P Figure 17-9 shows the same timing data, but with the prescaler enabled. Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-10 shows the setting of OCF2A in all modes except CTC mode. Figure 17-10.
ATmega329P/3290P Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRnx BOTTOM BOTTOM + 1 TOP OCFnx 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted.
ATmega329P/3290P user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2A, TCNT2, or OCR2A. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.
ATmega329P/3290P 17.9.1 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 PSR2 clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
ATmega329P/3290P 17.10 Register Description 17.10.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
ATmega329P/3290P When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting. Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 17-3. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match.
ATmega329P/3290P Table 17-6. 17.10.2 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega329P/3290P • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
ATmega329P/3290P 17.10.6 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – – OCF2A TOV2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega329P/3290P 18. SPI – Serial Peripheral Interface 18.1 Features • • • • • • • • 18.
ATmega329P/3290P The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2 on page 161. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega329P/3290P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 18-1. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 69. Table 18-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega329P/3290P The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega329P/3290P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega329P/3290P 18.3 18.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega329P/3290P Figure 18-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 18-4.
ATmega329P/3290P 18.5 18.5.1 Register Description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
ATmega329P/3290P • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 18-5. 18.5.
ATmega329P/3290P 18.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
ATmega329P/3290P 19. USART0 19.1 Features • • • • • • • • • • • • 19.
ATmega329P/3290P Figure 19-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
ATmega329P/3290P 19.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
ATmega329P/3290P Figure 19-2. .Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: 19.3.1 txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal).
ATmega329P/3290P Figure 19-3.
ATmega329P/3290P 19.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 19-4. Synchronous Mode XCK Timing.
ATmega329P/3290P St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
ATmega329P/3290P For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRR0H, r17 out UBRR0L, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega329P/3290P 19.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
ATmega329P/3290P 19.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega329P/3290P contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
ATmega329P/3290P bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSR0A & (1<
ATmega329P/3290P The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
ATmega329P/3290P 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega329P/3290P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 19.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate.
ATmega329P/3290P larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 19-6.
ATmega329P/3290P Figure 19-8. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega329P/3290P Table 19-1. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 19-2.
ATmega329P/3290P nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega329P/3290P 19.10 Register Description 19.10.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXBn[7:0] UDRn (Read) TXBn[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
ATmega329P/3290P • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
ATmega329P/3290P • Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
ATmega329P/3290P • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Figure 19-10.
ATmega329P/3290P Figure 19-13. UCPOLn Bit Settings Transmitted Data Changed (Output of TxD Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge UCPOLn 19.10.
ATmega329P/3290P Table 19-3. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz Baud Rate (bps) U2Xn = 0 UBRRn fosc = 1.8432MHz U2Xn = 1 Error UBRRn U2Xn = 0 Error UBRRn fosc = 2.0000MHz U2Xn = 1 Error U2Xn = 0 UBRRn Error UBRRn U2Xn = 1 Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.
ATmega329P/3290P Table 19-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.
ATmega329P/3290P Table 1. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz Baud Rate (bps) U2Xn = 0 U2Xn = 1 U2Xn = 0 fosc = 14.7456MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.
ATmega329P/3290P Table 2. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz Baud Rate (bps) U2Xn = 0 fosc = 18.4320MHz U2Xn = 1 U2Xn = 0 fosc = 20.0000MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.
ATmega329P/3290P 20. USI – Universal Serial Interface 20.1 Features • • • • • • 20.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wake up from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication.
ATmega329P/3290P The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges.
ATmega329P/3290P Figure 20-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 20-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATmega329P/3290P rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
ATmega329P/3290P 20.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATmega329P/3290P 20.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 20-4.
ATmega329P/3290P Figure 20-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 20-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A).
ATmega329P/3290P 20.3.5 Start Condition Detector The start condition detector is shown in Figure 20-6 The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATmega329P/3290P 20.5 20.5.1 Register Description USIDR – USI Data Register Bit 7 6 5 4 3 2 1 0 (0xBA) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
ATmega329P/3290P • Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. • Bit 4 – USIDC: Data Output Collision This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag is only valid when Two-wire mode is used.
ATmega329P/3290P Table 20-1. Relations between USIWM1:0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega329P/3290P Table 20-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 20-2.
ATmega329P/3290P 21. Analog Comparator 21.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega329P/3290P Table 21-1. 21.3 21.3.1 Analog Comparator Multiplexed Input (Continued) ACME ADEN MUX2..
ATmega329P/3290P • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
ATmega329P/3290P When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. 22. Analog to Digital Converter 22.1 Features • • • • • • • • • • • • • 22.2 10-bit Resolution 0.
ATmega329P/3290P Figure 22-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega329P/3290P If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega329P/3290P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 22.5 Prescaling and Conversion Timing Figure 22-3.
ATmega329P/3290P with Auto triggering from a source other than the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 22-1. Figure 22-4.
ATmega329P/3290P Figure 22-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 22-1. MUX and REFS Update ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 22.
ATmega329P/3290P 22.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega329P/3290P 22.7.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 22-8 An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
ATmega329P/3290P Figure 22-9. ADC Power Connections GND 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 10μΗ GND AVCC 100nF Analog Ground Plane 22.7.3 51 63 64 1 LCDCAP PA0 VCC ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
ATmega329P/3290P • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 22-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
ATmega329P/3290P • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 22-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
ATmega329P/3290P Figure 22-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 22-2. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 510 0x1FE 510 VADCm + /512 VREF Corresponding Decimal Value ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
ATmega329P/3290P 22.9 22.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 3.
ATmega329P/3290P Table 22-3.
ATmega329P/3290P 22.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega329P/3290P Table 22-5. 22.9.3 22.9.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 22.9.3.
ATmega329P/3290P • Bit 7 – Reserved This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag.
ATmega329P/3290P 23. LCD Controller 23.1 Features • • • • • • • • • • • • 23.
ATmega329P/3290P Figure 23-1.
ATmega329P/3290P To energize a segment, an absolute voltage above a certain threshold must be applied. This is done by letting the output voltage on corresponding COM pin and SEG pin have opposite phase. For display with more than one common, one (1/2 bias) or two (1/3 bias) additional voltage levels must be applied. Otherwise, non-energized segments on COM0 would be energized for all non-selected common.
ATmega329P/3290P mum drive time of approximately 2ms when using 1/2 or 1/4 duty, and approximately 2.7ms when using 1/3 duty. To achieve satisfactory contrast, all segments on the LCD display must therefore be able to be fully charged/discharged within 2 or 2.7ms, depending on the number of common pins. 23.2.9 Minimizing power consumption By keeping the percentage of the time the LCD drivers are turned on at a minimum, the power consumption of the LCD driver can be minimized.
ATmega329P/3290P Figure 23-4. Driving a LCD with Two Common Terminals VLCD VLCD SEG0 GND 1/ VLCD 2VLCD GND 1/ VLCD 2VLCD -1/ GND V 2 LCD -VLCD COM0 VLCD 1/ V 2 LCD COM1 GND VLCD 1/ V 2 LCD SEG0 - COM0 SEG0 - COM1 GND -1/ V 2 LCD -VLCD Frame 23.3.3 SEG0 GND Frame Frame Frame 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is shown in Figure 23-5.
ATmega329P/3290P Figure 23-6. Driving a LCD with Four Common Terminals VLCD 2/ 3VLCD 1/ 3VLCD VLCD SEG0 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD VLCD COM0 2/ 3VLCD 1/ 3VLCD GND 3VLCD 1/ 3VLCD GND -1/3VLCD -2/3VLCD -VLCD 23.3.
ATmega329P/3290P (TOSC1) pin instead of a 32kHz crystal. See ”Asynchronous Operation of Timer/Counter2” on page 152 for further details. Before entering Power-down mode, Standby mode or ADC Noise Reduction mode with synchronous LCD clock selected, the user have to disable the LCD. Refer to ”Disabling the LCD” on page 239. 23.3.7 Display Blanking When LCDBL is written to one, the LCD is blanked after completing the current frame. All segments and common pins are connected to GND, discharging the LCD.
ATmega329P/3290P 23.4 LCD Usage The following section describes how to use the LCD. 23.4.1 LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization process normally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but can also be adjusted during operation. Consider the following LCD as an example: Figure 23-8.
ATmega329P/3290P Assembly Code Example(1) LCD_Init: ; Use 32kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1<
ATmega329P/3290P 23.4.2 Updating the LCD Display memory (LCDDR0, LCDDR1,...), LCD Blanking (LCDBL), Low power waveform (LCDAB) and contrast control (LCDCCR) are latched prior to every new frame. There are no restrictions on writing these LCD Register locations, but an LCD data update may be split between two frames if data are latched while an update is in progress.
ATmega329P/3290P Assembly Code Example(1) LCD_disable: ; Wait until a new frame is started. Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; Set LCD Blanking and clear interrupt flag ; by writing a logical one to the flag. ldi r16, (1<
ATmega329P/3290P 23.5 23.5.1 Register Description LCDCRA – LCD Control and Status Register A Bit 7 6 5 4 3 2 1 0 LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL Read/Write R/W R/W R R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 (0xE4) LCDCRA • Bit 7 – LCDEN: LCD Enable Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned off immediately.
ATmega329P/3290P • Bit 0 – LCDBL: LCD Blanking When this bit is written to one, the display will be blanked after completion of a frame. All segment and common pins will be driven to ground. 23.5.2 LCDCRB – LCD Control and Status Register B Bit 7 6 5 4 3 2 1 0 LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xE5) Note: LCDCRB Bit 3, LCDPM3 is only available in ATmega3290P.
ATmega329P/3290P Table 23-3. LCDPM3 LCDPM2 LCDPM1 LCDPM0 I/O Port in Use as Segment Driver Maximum Number of Segments 0 1 0 0 SEG0:20 21 0 1 0 1 SEG0:22 23 0 1 1 0 SEG0:23 24 0 1 1 1 SEG0:24 25 1 0 0 0 SEG0:26 27 1 0 0 1 SEG0:28 29 1 0 1 0 SEG0:30 31 1 0 1 1 SEG0:32 33 1 1 0 0 SEG0:34 35 1 1 0 1 SEG0:36 37 1 1 1 0 SEG0:38 39 1 1 1 1 SEG0:39 40 Note: 23.5.
ATmega329P/3290P Table 23-4. LCD Prescaler Select (Continued) LCDPS2 LCDPS1 LCDPS0 Output from Prescaler clkLCD/N Applied Prescaled LCD Clock Frequency when LCDCD2:0 = 0, Duty = 1/4, and Frame Rate = 64 Hz 1 0 1 clkLCD/1024 520kHz 1 1 0 clkLCD/2048 1MHz 1 1 1 clkLCD/4096 2MHz • Bit 3 – Reserved This bit is reserved and will always read as zero. • Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0 The LCDCD2:0 bits determine division ratio in the clock divider.
ATmega329P/3290P is increased with 33% when Frame Rate Register is constant. Example of frame rate calculation is shown in Table 23-6 on page 245. Table 23-6. 23.5.4 Example of frame rate calculation clkLCD duty K N LCDCD2:0 D Frame Rate 4MHz 1/4 8 2048 011 4 4000000/(8*2048*4) = 61Hz 4MHz 1/3 6 2048 011 4 4000000/(6*2048*4) = 81Hz 32.768kHz Static 8 16 000 1 32768/(8*16*1) = 256Hz 32.
ATmega329P/3290P • Bits 3:0 – LCDCC3:0: LCD Contrast Control The LCDCC3:0 bits determine the maximum voltage VLCD on segment and common pins. The different selections are shown in Table 23-8 on page 246. New values take effect every beginning of a new frame. Table 23-8. LCD Contrast Control LCDCC3 LCDCC2 LCDCC1 LCDCC0 Maximum Voltage VLCD 0 0 0 0 2.60 0 0 0 1 2.65 0 0 1 0 2.70 0 0 1 1 2.75 0 1 0 0 2.80 0 1 0 1 2.85 0 1 1 0 2.90 0 1 1 1 2.95 1 0 0 0 3.
ATmega329P/3290P 23.5.5 LCD Memory Mapping Write a LCD memory bit to one and the corresponding segment will be energized (visible). Unused LCD Memory bits for the actual display can be used freely as storage.
ATmega329P/3290P 24. JTAG Interface and On-chip Debug System 24.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega329P/3290P • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset.
ATmega329P/3290P Figure 24-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.
ATmega329P/3290P • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega329P/3290P A debugger, like the AVR Studio®, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 252. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
ATmega329P/3290P The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.
ATmega329P/3290P 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
ATmega329P/3290P 25.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
ATmega329P/3290P Figure 25-1. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 25.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 257 for a complete description. 25.
ATmega329P/3290P The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 25.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega329P/3290P Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 25-3 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. Figure 25-2.
ATmega329P/3290P Figure 25-3. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR WDx RESET OCxn DATA BUS RDx Pxn 1 Q ODxn IDxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 25.5.
ATmega329P/3290P 25.5.3 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 25-5 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
ATmega329P/3290P 25.5.4 Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 25-6. The Boundary-scan cell from Figure 25-7 is attached to each of these signals. The signals are described in Table 25-3. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 25-6. Analog Comparator BANDGAP REFERENCE ACBG ACD ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 25-7.
ATmega329P/3290P Table 25-3. 25.5.
ATmega329P/3290P Table 25-4.
ATmega329P/3290P Table 25-4.
ATmega329P/3290P • The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: The upper limit is: 1024 ⋅ 1.5V ⋅ 0,95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1.5V ⋅ 1.05 ⁄ 5V = 323 = 0x143 The recommended values from Table 25-4 are used unless other values are given in the algorithm in Table 25-5.
ATmega329P/3290P 25.6 ATmega329P/3290P Boundary-scan Order Table 25-6 and Table 25-7 shows the Scan order between TDI and TDO when the Boundaryscan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
ATmega329P/3290P Table 25-6.
ATmega329P/3290P Table 25-6. ATmega329P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.Control 137 PE6.
ATmega329P/3290P Table 25-6. ATmega329P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 133 PB0.Data 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.Control 113 PB6.
ATmega329P/3290P Table 25-6. ATmega329P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 100 EXTCLKEN 99 OSCON 98 RCOSCEN 97 OSC32EN 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.
ATmega329P/3290P Table 25-6. ATmega329P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 64 PG1.Control 63 PG1.Pull-up_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.
ATmega329P/3290P Table 25-6. ATmega329P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.
ATmega329P/3290P Table 25-7.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.Data 186 PE5.Control 185 PE5.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.Control 152 PB6.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 135 EXTCLK (XTAL1) 134 OSCCK 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.Control 117 PJ6.Pull-up_Enable 116 PD0.Data 115 PD0.Control 114 PD0.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.Data 79 PC2.Control 78 PC2.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.Data 43 PA6.Control 42 PA6.
ATmega329P/3290P Table 25-7. ATmega3290P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.
ATmega329P/3290P 25.8 25.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
ATmega329P/3290P 26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 26.2 1. A page is a section in the Flash consisting of several bytes (see Table 27-13 on page 301) used during programming.
ATmega329P/3290P 26.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega329P/3290P Figure 26-1. Read-While-Write vs.
ATmega329P/3290P Figure 26-2.
ATmega329P/3290P Table 26-2. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
ATmega329P/3290P 26.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.
ATmega329P/3290P Figure 26-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: 26.8 1. The different variables used in Figure 26-3 on page 287 are listed in Table 26-8 on page 293. 2. PCPAGE and PCWORD are listed in Table 27-13 on page 301.
ATmega329P/3290P 26.8.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase.
ATmega329P/3290P RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example for a Boot Loader” on page 291 for an example. 26.8.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
ATmega329P/3290P Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 27-3 on page 297 for detailed description and mapping of the Extended Fuse byte.
ATmega329P/3290P 26.8.12 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
ATmega329P/3290P brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega329P/3290P Table 26-7. Read-While-Write Limit (ATmega329P/3290P)(1) Section Pages Address Read-While-Write section (RWW) 224 0x0000 - 0x37FF No Read-While-Write section (NRWW) 32 0x3800 - 0x3FFF Note: 1. For details about these two section, see ”NRWW – No Read-While-Write Section” on page 282 and ”RWW – Read-WhileWrite Section” on page 282. Table 26-8.
ATmega329P/3290P 26.9 26.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega329P/3290P taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase.
ATmega329P/3290P 27. Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega329P/3290P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1.
ATmega329P/3290P Lock Bit Protection Modes(1)(2) (Continued) Table 27-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega329P/3290P Table 27-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega329P/3290P 27.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 27.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega329P/3290P 27.6.1 Signal Names In this section, some pins of the ATmega329P/3290P are referenced by signal names describing their functionality during parallel programming, see Figure 27-1 and Table 27-9. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 27-11. When pulsing WR or OE, the command loaded determines the action executed.
ATmega329P/3290P Table 27-10. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 Table 27-11. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 27-12.
ATmega329P/3290P 27.7 27.7.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) Programming mode: 1. Set Prog_enable pins listed in Table 27-10 on page 301 to “0000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Ensure that VCC reaches at least 1.8V within the next 20 µs. 4. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 5.
ATmega329P/3290P 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 27.7.4 Programming the Flash The Flash is organized in pages, see Table 27-13 on page 301. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously.
ATmega329P/3290P H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 27-3 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse.
ATmega329P/3290P Figure 27-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 1. “XX” is don’t care. The letters refer to the programming description above.
ATmega329P/3290P 27.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 27-14 on page 301. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 303 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
ATmega329P/3290P 27.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 303 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 27.7.
ATmega329P/3290P Figure 27-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 27.7.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 303 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
ATmega329P/3290P Figure 27-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte 1 BS1 BS2 27.7.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 303 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
ATmega329P/3290P Table 27-15. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low WR Low to RDY/BSY High tWLRH (1) (2) Max Units 0 1 μs 3.7 4.5 ms 7.
ATmega329P/3290P Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 27-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 27-9.
ATmega329P/3290P 27.7.16 Serial Programming Pin Mapping Table 27-16. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB2 I Serial Data in MISO PB3 O Serial Data out SCK PB1 I Serial Clock Figure 27-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.
ATmega329P/3290P tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync.
ATmega329P/3290P Figure 27-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 27.7.18 Serial Programming Instruction set Table 27-18 and Figure 27-12 on page 316 describes the Instruction set. Table 27-18.
ATmega329P/3290P Table 27-18.
ATmega329P/3290P Figure 27-12. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB A Bit 15 B Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 27.7.
ATmega329P/3290P 27.8 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
ATmega329P/3290P Figure 27-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.8.
ATmega329P/3290P 27.8.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
ATmega329P/3290P 27.8.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific JTAG Instructions” on page 317. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 27.8.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
ATmega329P/3290P Figure 27-15.
ATmega329P/3290P Table 27-19. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega329P/3290P Table 27-19. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b.
ATmega329P/3290P Table 27-19. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
ATmega329P/3290P Figure 27-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.8.
ATmega329P/3290P ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 27-17.
ATmega329P/3290P 27.8.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-15 on page 309). 27.8.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 327. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
ATmega329P/3290P 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 27-13 on page 301) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash).
ATmega329P/3290P 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-15 on page 309). 27.8.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5.
ATmega329P/3290P 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
ATmega329P/3290P Table 28-1. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min.
ATmega329P/3290P 28.2.1 ATmega329P DC Characteristics Table 28-2. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Parameter Power Supply Current ICC Power-save mode Power-down mode(1) Notes: Condition Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.5 0.75 mA Active 4MHz, VCC = 3V 2.6 3.5 mA Active 8MHz, VCC = 5V 9 12 mA Idle 1MHz, VCC = 2V 0.14 0.25 mA Idle 4MHz, VCC = 3V 0.75 1.5 mA Idle 8MHz, VCC = 5V 2.9 5 mA 32kHz TOSC enabled, VCC = 1.8V 0.
ATmega329P/3290P 28.2.2 ATmega3290P DC Characteristics TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Table 28-3. Symbol Parameter Condition Power Supply Current ICC Power-save mode Power-down mode(1) Note: 1. Typical value at 25°C 28.3 Speed Grades Min. Typ. Max. Units Active 1MHz, VCC = 2V 0.5 0.75 mA Active 4MHz, VCC = 3V 2.6 3.5 mA Active 8MHz, VCC = 5V 9 12 mA Idle 1MHz, VCC = 2V 0.14 0.25 mA Idle 4MHz, VCC = 3V 0.75 1.5 mA Idle 8MHz, VCC = 5V 2.
ATmega329P/3290P Figure 28-2. Maximum Frequency vs. VCC (4 - 10MHz) 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 28-3. Maximum Frequency vs. VCC (10 - 20MHz) 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.
ATmega329P/3290P 28.4 28.4.1 Clock Characteristics Calibrated Internal RC Oscillator Accuracy Table 28-4. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0MHz 3V 25°C ±10% User Calibration 7.3 - 8.1MHz 1.8V - 5.5V(1) -40°C - 85°C ±1% Notes: 28.4.2 1. Voltage range for ATmega329P/3290P External Clock Drive Waveforms Figure 28-4. External Clock Drive Waveforms V IH1 V IL1 28.4.3 External Clock Drive Table 28-5.
ATmega329P/3290P 28.5 System and Reset Characteristics Table 28-6. Symbol Parameter Condition Min 0.2 VCC VRST RESET Pin Threshold Voltage VCC = 3V tRST Minimum pulse width on RESET Pin VCC = 3V Typ Max Units 0.9 VCC V 2.5 µs VHYST Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 2.7V, TA = 25°C tBG Bandgap reference start-up time IBG Bandgap reference current consumption Note: 28.
ATmega329P/3290P 28.7 Enhanced Power-on Reset This implementation of power-on reset exists in newer versions of ATmega329P/ATmega3290P. The table below describes the characteristics of this power-on reset and it is valid for the following devices only: • ATmega329P revision C and newer • ATmega3290P revision C and newer Table 28-8. Reset, Brown-out and Internal Voltage Reference Characteristics(1), TA = -40°C to 85°C Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT SRON Notes: 28.
ATmega329P/3290P 28.9 SPI Timing Characteristics See Figure 28-5 and Figure 28-6 for details. Table 28-10. SPI Timing Parameters Description Mode 1 SCK period Master See Table 18-5 on page 168 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega329P/3290P Figure 28-6. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega329P/3290P 28.10 ADC Characteristics – Preliminary Data Table 28-11. ADC Characteristics Symbol Parameter Condition Min. Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 2.
ATmega329P/3290P Table 28-11. ADC Characteristics Symbol Parameter Condition Min. Typ Max Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Notes: 1. Voltage difference between channels 28.11 LCD Controller Characteristics Table 28-12. LCD Controller Characteristics Symbol Parameter ILCD LCD Driver Current RSEG RCOM Condition Total for All COM and SEG pins Min.
ATmega329P/3290P 29. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
ATmega329P/3290P 29.1 29.1.1 ATmega329P Active Supply Current Figure 29-1. ATmega329P: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.8 5.5 V 1.6 5.0 V 1.4 4.5 V ICC (mA) 1.2 4.0 V 1 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-2. ATmega329P: Active Supply Current vs. Frequency (1 - 20MHz) 25 5.5 V 5.0 V 20 ICC (mA) 4.5 V 15 4.0 V 10 3.3 V 5 2.7 V 1.
ATmega329P/3290P Figure 29-3. ATmega329P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz 12 85 °C 25 °C -40 °C 10 I CC(mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-4. )ATmega329P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 85 °C 2 25 °C ICC (mA) -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-5. ATmega329P: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 85 °C 25 °C -40 °C 35 30 Icc (mA) 25 20 15 10 5 0 0 1.8 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 29.1.2 Idle Supply Current Figure 29-6. ATmega329P: Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.6 0.5 5.5 V 5.0 V 0.4 ICC (mA) 4.5 V 4.0 V 0.3 3.3 V 0.2 2.7 V 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega329P/3290P Figure 29-7. ATmega329P: Idle Supply Current vs. Frequency (1 - 20MHz) 8 5.5V 7 5.0V 6 4.5V ICC (mA) 5 4.0V 4 3 3.3V 2 2.7V 1 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 29-8. ATmega329P: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 85 °C 25 °C -40 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-9. ATmega329P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 85 °C 0.8 25 °C 0.7 -40 °C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.1.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
ATmega329P/3290P It is possible to calculate the typical current consumption based on the numbers from Table 29-2 for other VCC and frequency settings than listed in Table 29-1. 29.1.4 Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 29-2 shows that we need to add 4.9% for the USART0, 5.9% for the SPI, and 2.6% for the TIMER1 module. From Figure 29-6, we find that the idle current consumption is ~0.21mA at VCC = 3.
ATmega329P/3290P Figure 29-11. ATmega329P: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 18 -40 °C 16 25 °C 14 ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.1.6 Power-save Supply Current Figure 29-12. ATmega329P: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 3.5 85 °C 3 ICC (uA) 2.5 2 1.5 25 °C 1 -40 °C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.1.7 Standby Supply Current Figure 29-13. ATmega329P: Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.2 0.18 6MHz_xtal 6MHz_res 0.16 0.14 4MHz_res 4MHz_xtal ICC(mA) 0.12 0.1 2MHz_res 2MHz_xtal 1MHz_res 450kHz_res 0.08 0.06 0.04 0.02 32kHz_xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (MHz) 29.1.8 Pin Pull-up Figure 29-14. ATmega329P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.
ATmega329P/3290P Figure 29-15. ATmega329P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 29-16. ATmega329P: I/O Pin Pull-up Resistor Current vs.
ATmega329P/3290P Figure 29-17. ATmega329P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 30 IRESET(uA) 25 20 15 10 25 °C -40 °C 5 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 29-18. ATmega329P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 IRESET(uA) 50 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-19. ATmega329P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET(uA) 80 60 40 25 °C 20 -40 °C 85 °C 0 0 1 2 3 4 5 6 VRESET(V) 29.1.9 Pin Driver Strength Figure 29-20. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) 14 12 -40 °C 10 25 °C IOL (mA) 85 °C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega329P/3290P Figure 29-21. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7 V) 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 29-22. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) 80 70 60 25 °C IOL (mA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-23. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 1.8 V) 7 6 -40 °C 5 25 °C IOL (mA) 85 °C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) Figure 29-24. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 2.7V) 16 14 25 °C 12 IOL (mA) 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-25. ATmega329P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 5 V) 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 29-26. ATmega329P: I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8V) 8 -40 °C 7 25 °C 6 85 °C IOH (mA) 5 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.
ATmega329P/3290P Figure 29-27. ATmega329P: I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V) 25 25 °C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 29-28. ATmega329P: I/O Pin Source Current vs.
ATmega329P/3290P Figure 29-29. ATmega329P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=1.8V) 6 -40 °C 5 25 °C 85 °C IOH (mA) 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 VOH (V) Figure 29-30. ATmega329P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J(VCC=2.7V) 20 18 16 14 IOH (mA) 25 °C 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-31. ATmega329P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=5V) 60 50 25 °C IOH (mA) 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) 29.1.10 Pin Threshold and Hysteresis Figure 29-32. ATmega329P: I/O Pin Input Threshold Voltage vs. VCC, Port B (VIH, IO Pin Read as ¨1¨) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-33. ATmega329P: I/O Pin Input Threshold Voltage vs. VCC, Port B (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C Threshold (V) 2 -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-34. ATmega329P: I/O Pin Input Hysteresis vs. VCC, Port B 0.7 0.6 -40 °C Input Hysteresis (V) 0.5 25 °C 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-35. ATmega329P: I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIH, IO Pin Read as ¨1¨) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-36. ATmega329P: I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-37. ATmega329P: I/O Pin Hysteresis vs. VCC, Port A,C,D,E,F,G,H,J 0.7 0.6 -40 °C 25 °C Input Hysteresis (V) 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-38. ATmega329P: Reset Input Threshold Voltage vs. VCC(VIH, IO Pin Read as ¨1¨) 2.5 -40 °C 25 °C Threshold (V) 2 85 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-39. ATmega329P: Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-40. ATmega329P: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -40 °C 0.1 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.1.11 Internal Oscillator Speed Figure 29-41. ATmega329P: Watchdog Oscillator Frequency vs. VCC 1300 -45 °C 25 °C 85 °C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-42. ATmega329P: Watchdog Oscillator Frequency vs. Temperature 170 165 FRC (kHz) 160 5.5 V 155 4.0 V 150 3.3 V 2.7 V 145 2.
ATmega329P/3290P Figure 29-43. ATmega329P: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.4 85 °C 8.2 25 °C FRC (MHz) 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5,5 VCC (V) Figure 29-44. ATmega329P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature FRC (MHz) 8.4 8.2 5.5 V 4.0 V 3.3 V 2.7 V 8 1.8 V 7.8 7.6 7.
ATmega329P/3290P Figure 29-45. ATmega329P: Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 85 °C 14 25 °C 12 -40 °C FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 29.1.12 Current Consumption of Peripheral Units Figure 29-46. ATmega329P: Brownout Detector Current vs. VCC 25 85 °C 24 23 25 °C 22 -40 °C ICC (µA) 21 20 19 18 17 16 15 14 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-47. ATmega329P: Active Supply Current with ADC at 50kHz vs. Vcc 350 -40 °C 85 °C 25 °C 330 310 290 ICC [uA] 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 29-48. ATmega329P: Active Supply Current with ADC at 200kHz vs. Vcc 350 -40 °C 85 °C 25 °C 330 310 290 ICC [uA] 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-49. ATmega329P: Active Supply Current with ADC at 1MHz vs. Vcc 350 85 °C 25 °C -45 °C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-50. ATmega329P: ADC Current vs. VCC (AREF = AVCC) 360 -40 °C 25 °C 85 °C 340 320 300 ICC (µA) 280 260 240 220 200 180 160 140 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-51. ATmega329P: AREF External Reference Current vs. VCC 180 -40 °C 160 25 °C 140 85 °C ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-52. ATmega329P: Watchdog Timer Current vs. VCC 18 -40 °C 16 85 °C 14 25 °C ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-53. ATmega329P: Analog Comparator Current vs. VCC 100 90 -40 °C 80 25 °C 85 °C 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-54. ATmega329P: Programming Current vs. VCC 12 -40 °C 25 °C 10 85 °C ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.1.13 Current Consumption in Reset and Reset Pulswidth Figure 29-55. ATmega329P: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.25 5.5 V 0.2 5.0 V ICC (mA) 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-56. ATmega329P: Reset Supply Current vs. Frequency (1 - 20MHz) 4 5.5 V 3.5 5.0 V 3 4.5 V ICC (mA) 2.5 4.0 V 2 1.5 3.6 V 1 3.3 V 0.5 1.
ATmega329P/3290P Figure 29-57. ATmega329P: Minimum Reset Pulse Width vs. VCC 2200 2000 Pulsewidth (ns) 1800 1600 1400 1200 1000 800 600 85 °C 25 °C -40 °C 400 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.2 29.2.1 ATmega3290P Active Supply Current Figure 29-58. ATmega3290P: Active Supply Current vs. Low Frequency (0.1 - 1.0MHz) 1.8 5.5 V 1.6 5.0 V 1.4 4.5 V ICC (mA) 1.2 4.0 V 1 0.8 3.3 V 0.6 2.7 V 0.4 1.8 V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-59. ATmega3290P: Active Supply Current vs. Frequency (1 - 20MHz) 25 5.5 V 5.0 V 20 ICC (mA) 4.5 V 15 4.0 V 10 3.3 V 5 2.7 V 1.
ATmega329P/3290P Figure 29-60. ATmega3290P: Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz 12 85 °C 25 °C -40 °C 10 I CC(mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-61. )ATmega3290P: Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 2.5 85 °C 2 25 °C ICC (mA) -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-62. ATmega3290P: Active Supply Current vs. VCC (32kHz Watch Crystal) 40 85 °C 25 °C -40 °C 35 30 Icc (mA) 25 20 15 10 5 0 0 1.8 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 29.2.2 Idle Supply Current Figure 29-63. ATmega3290P: Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.6 0.5 5.5 V 5.0 V 0.4 ICC (mA) 4.5 V 4.0 V 0.3 3.3 V 0.2 2.7 V 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega329P/3290P Figure 29-64. ATmega3290P: Idle Supply Current vs. Frequency (1 - 20MHz) 8 5.5V 7 5.0V 6 4.5V ICC (mA) 5 4.0V 4 3 3.3V 2 2.7V 1 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 29-65. ATmega3290P: Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 3.5 85 °C 25 °C -40 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-66. ATmega3290P: Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.9 85 °C 0.8 25 °C 0.7 -40 °C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.2.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
ATmega329P/3290P It is possible to calculate the typical current consumption based on the numbers from Table 29-4 for other VCC and frequency settings than listed in Table 29-3. 29.2.4 Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 29-4 shows that we need to add 4.9% for the USART0, 5.9% for the SPI, and 2.6% for the TIMER1 module. From Figure 29-63, we find that the idle current consumption is ~0.21mA at VCC = 3.
ATmega329P/3290P Figure 29-68. ATmega3290P: Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C 18 -40 °C 16 25 °C 14 ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.2.6 Power-save Supply Current Figure 29-69. ATmega3290P: Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 3.5 85 °C 3 ICC (uA) 2.5 2 1.5 25 °C 1 -40 °C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.2.7 Standby Supply Current Figure 29-70. ATmega3290P: Standby Supply Current vs. VCC (Watchdog Timer Disabled) 0.2 0.18 6MHz_xtal 6MHz_res 0.16 0.14 4MHz_res 4MHz_xtal ICC(mA) 0.12 0.1 2MHz_res 2MHz_xtal 1MHz_res 450kHz_res 0.08 0.06 0.04 0.02 32kHz_xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (MHz) 29.2.8 Pin Pull-up Figure 29-71. ATmega3290P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 IOP (uA) 40 30 20 10 25 °C -40 °C 85 °C 0 0 0.2 0.
ATmega329P/3290P Figure 29-72. ATmega3290P: I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 80 70 60 IOP (uA) 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 29-73. ATmega3290P: I/O Pin Pull-up Resistor Current vs.
ATmega329P/3290P Figure 29-74. ATmega3290P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 35 30 IRESET(uA) 25 20 15 10 25 °C -40 °C 5 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) Figure 29-75. ATmega3290P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 IRESET(uA) 50 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-76. ATmega3290P: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 120 100 IRESET(uA) 80 60 40 25 °C 20 -40 °C 85 °C 0 0 1 2 3 4 5 6 VRESET(V) 29.2.9 Pin Driver Strength Figure 29-77. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) 14 12 -40 °C 10 25 °C IOL (mA) 85 °C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega329P/3290P Figure 29-78. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V) 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 29-79. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) 80 70 60 25 °C IOL (mA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-80. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=1.8V) 7 6 -40 °C 5 25 °C IOL (mA) 85 °C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) Figure 29-81. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 2.7V) 16 14 25 °C 12 IOL (mA) 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-82. ATmega3290P: I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=5V) 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 29-83. ATmega3290P: I/O Pin Source Current vs. Output Voltage, Port B (VCC=1.8V) 8 -40 °C 7 25 °C 6 85 °C IOH (mA) 5 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.
ATmega329P/3290P Figure 29-84. ATmega3290P: I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V) 25 25 °C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 29-85. ATmega3290P: I/O Pin Source Current vs.
ATmega329P/3290P Figure 29-86. ATmega3290P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=1.8V) 6 -40 °C 5 25 °C 85 °C IOH (mA) 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 VOH (V) Figure 29-87. ATmega3290P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=2.7V) 20 18 16 14 IOH (mA) 25 °C 12 10 8 6 4 2 0 0 0.5 1 1.5 2 2.
ATmega329P/3290P Figure 29-88. ATmega3290P: I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC=5V) 60 50 25 °C IOH (mA) 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) 29.2.10 Pin Threshold and Hysteresis Figure 29-89. ATmega3290P: I/O Pin Input Threshold Voltage vs. VCC, Port B (VIH, IO Pin Read as ¨1¨) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-90. ATmega3290P: I/O Pin Input Threshold Voltage vs. VCC, Port B (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C Threshold (V) 2 -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-91. ATmega3290P: I/O Pin Input Hysteresis vs. VCC, Port B 0.7 0.6 -40 °C Input Hysteresis (V) 0.5 25 °C 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-92. ATmega3290P: I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIH, IO Pin Read as ¨1¨) 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-93. ATmega3290P: I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-94. ATmega3290P: I/O Pin Hysteresis vs. VCC, Port A,C,D,E,F,G,H,J 0.7 0.6 -40 °C 25 °C Input Hysteresis (V) 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-95. ATmega3290P: Reset Input Threshold Voltage vs. VCC(VIH, IO Pin Read as ¨1¨) 2.5 -40 °C 25 °C Threshold (V) 2 85 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-96. ATmega3290P: Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ¨0¨) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-97. ATmega3290P: Reset Pin Input Hysteresis vs. VCC 0.7 0.6 Input Hysteresis (V) 0.5 0.4 0.3 0.2 -40 °C 0.1 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.2.11 Internal Oscillator Speed Figure 29-98. ATmega3290P: Watchdog Oscillator Frequency vs. VCC 1300 -45 °C 25 °C 85 °C 1250 FRC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-99. ATmega3290P: Watchdog Oscillator Frequency vs. Temperature 170 165 FRC (kHz) 160 5.5 V 155 4.0 V 150 3.3 V 2.7 V 145 2.
ATmega329P/3290P Figure 29-100.ATmega3290P: Calibrated 8MHz RC Oscillator Frequency vs. VCC 8.4 85 °C 8.2 25 °C FRC (MHz) 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5,5 VCC (V) Figure 29-101.ATmega3290P: Calibrated 8MHz RC Oscillator Frequency vs. Temperature FRC (MHz) 8.4 8.2 5.5 V 4.0 V 3.3 V 2.7 V 8 1.8 V 7.8 7.6 7.
ATmega329P/3290P Figure 29-102.ATmega3290P: Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 16 85 °C 14 25 °C 12 -40 °C FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 29.2.12 Current Consumption of Peripheral Units Figure 29-103.ATmega3290P: Brownout Detector Current vs. VCC 25 85 °C 24 23 25 °C 22 -40 °C ICC (µA) 21 20 19 18 17 16 15 14 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-104.ATmega3290P: Active Supply Current with ADC at 50kHz vs. Vcc 350 -40 °C 85 °C 25 °C 330 310 290 ICC [uA] 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC [V] Figure 29-105.ATmega3290P: Active Supply Current with ADC at 200kHz vs. Vcc 350 -40 °C 85 °C 25 °C 330 310 290 ICC [uA] 270 250 230 210 190 170 150 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-106.ATmega3290P: Active Supply Current with ADC at 1MHz vs. Vcc 350 85 °C 25 °C -45 °C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-107.ATmega3290P: ADC Current vs. VCC (AREF = AVCC) 360 -40 °C 25 °C 85 °C 340 320 300 ICC (µA) 280 260 240 220 200 180 160 140 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-108.ATmega3290P: AREF External Reference Current vs. VCC 180 -40 °C 160 25 °C 140 85 °C ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-109.ATmega3290P: Watchdog Timer Current vs. VCC 18 -40 °C 16 85 °C 14 25 °C ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P Figure 29-110.ATmega3290P: Analog Comparator Current vs. VCC 100 90 -40 °C 80 25 °C 85 °C 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-111.ATmega3290P: Programming Current vs. VCC 12 -40 °C 25 °C 10 85 °C ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 29.2.13 Current Consumption in Reset and Reset Pulswidth Figure 29-112.ATmega3290P: Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.25 5.5 V 0.2 5.0 V ICC (mA) 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-113.ATmega3290P: Reset Supply Current vs. Frequency (1 - 20MHz) 4 5.5 V 3.5 5.0 V 3 4.5 V ICC (mA) 2.5 4.0 V 2 1.5 3.6 V 1 3.3 V 0.5 1.
ATmega329P/3290P Figure 29-114.ATmega3290P: Minimum Reset Pulse Width vs. VCC 2200 2000 Pulsewidth (ns) 1800 1600 1400 1200 1000 800 600 85 °C 25 °C -40 °C 400 200 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega329P/3290P 30. Register Summary Note: Address Name Registers with bold type only available in ATmega3290P.
ATmega329P/3290P Address Name (0xC4) UBRR0L (0xC3) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - USART0 Baud Rate Register Low - - - - - Page 193 (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191 190 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 189 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserve
ATmega329P/3290P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x85) TCNT1H Timer/Counter1 High (0x84) TCNT1L Timer/Counter1 Low (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 130 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 129 127 - - 131 131 - - - (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 212 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D
ATmega329P/3290P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - COM0A0 WGM01 CS02 CS01 CS00 136 - - - PSR2 PSR10 140/159 - - - 0x26 (0x46) TCNT0 Timer/Counter0 0x25 (0x45) Reserved - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 0x23 (0x43) GTCCR TSM - - 0x22 (0x42) EEARH - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - Page 138 EERIE EEPROM Address Registe
ATmega329P/3290P 31.
ATmega329P/3290P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left R
ATmega329P/3290P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega329P/3290P 32. Ordering Information 32.1 ATmega329P Speed (MHz)(3) 10 20 20 Notes: Power Supply Ordering Code(2) Package Type(1) 1.8 - 5.5V ATmega329PV-10AU ATmega329PV-10AUR(4) ATmega329PV-10MU ATmega329PV-10MUR(4) 64A 64A 64M1 64M1 2.7 - 5.5V ATmega329P-20AU ATmega329P-20AUR(4) ATmega329P-20MU ATmega329P-20MUR(4) 64A 64A 64M1 64M1 1.8 - 5.
ATmega329P/3290P 32.2 ATmega3290P Speed (MHz)(3) Power Supply Ordering Code(2) 10 1.8 - 5.5V ATmega3290PV-10AU ATmega3290PV-10AUR(4) 20 20 Notes: 2.7 - 5.5V ATmega3290P-20AU ATmega3290P-20AUR(4) 1.8 - 5.5V ATmega3290P-AN ATmega3290P-ANR(4) ATmega3290P-MN ATmega3290P-MNR(4) Package Type(1) 100A 64A 64A 64M1 64M1 Operational Range Industrial (-40°C to 85°C) Extended (-40°C to 105°C)(5) 1. This device can also be supplied in wafer form.
ATmega329P/3290P 412 8021G–AVR–03/11
ATmega329P/3290P 33. Packaging Information 33.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.
ATmega329P/3290P 33.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e BOTTOM VIEW Notes: Pin #1 Notch (0.20 R) D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.35 0.
ATmega329P/3290P 33.3 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.
ATmega329P/3290P 34. Errata 34.1 ATmega329P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer • Using BOD disable will make the chip reset 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega329P/3290P 34.4 ATmega3290P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer • Using BOD disable will make the chip reset 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega329P/3290P 35. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 35.1 Rev.8021G - 03/11 1. 2. 3. 4. 4. 5. 35.2 Rev.8021F - 02/11 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 35.3 Removed ATmega169PA/649P/6490P from the datasheet and updated it accordingly. Updated Feature Overviews.
ATmega329P/3290P 35.4 Rev.8021D – 06/08 1. 2. 3. 4. 5. 6. 7. 8. 35.5 Rev.8021C – 08/07 1. 35.6 Updated.”Errata” on page 416. Rev.8021B – 08/07 1. 2. 3. 35.7 Added ”Data Retention” on page 9. Updated description of ”Stack Pointer” on page 14. Updated description of ”Low-frequency Crystal Oscillator” on page 30. Added notes to the overview section of ”External Interrupts” on page 58. Updated address of ”PORTA – Port A Data Register” on page 90.
ATmega329P/3290P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 2.1Block Diagram ...........................................................................................................4 2.
ATmega329P/3290P 8.7External Clock .........................................................................................................32 8.8Clock Output Buffer .................................................................................................33 8.9Timer/Counter Oscillator .........................................................................................33 8.10System Clock Prescaler ........................................................................................33 8.
ATmega329P/3290P 13.3Alternate Port Functions ........................................................................................69 13.4Register Description ..............................................................................................90 14 8-bit Timer/Counter0 with PWM ............................................................ 94 14.1Features ................................................................................................................94 14.2Overview ..............
ATmega329P/3290P 17.10Register Description ..........................................................................................155 18 SPI – Serial Peripheral Interface ......................................................... 160 18.1Features ..............................................................................................................160 18.2Overview .............................................................................................................160 18.
ATmega329P/3290P 22.5Prescaling and Conversion Timing ......................................................................216 22.6Changing Channel or Reference Selection .........................................................218 22.7ADC Noise Canceler ...........................................................................................219 22.8ADC Conversion Result ......................................................................................223 22.9Register Description ....................
ATmega329P/3290P 26.4Read-While-Write and No Read-While-Write Flash Sections ..............................282 26.5Boot Loader Lock Bits .........................................................................................284 26.6Entering the Boot Loader Program ......................................................................286 26.7Addressing the Flash During Self-Programming .................................................286 26.8Self-Programming the Flash ......................................
ATmega329P/3290P 32.2ATmega3290P ....................................................................................................411 33 Packaging Information ........................................................................ 413 33.164A ......................................................................................................................413 33.264M1 ...................................................................................................................414 33.3100A .....
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