Data Sheet

208
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
22.2.1 TWI Terminology
The following definitions are frequently encountered in this section.
The PRTWI bit in ”Minimizing Power Consumption” on page 43 must be written to zero to enable the 2-wire
Serial Interface.
22.2.2 Electrical Interconnection
As depicted in Figure 22-1, both bus lines are connected to the positive supply voltage through pull-up resistors.
The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND
function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one
or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing
the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered
in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF
and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in
”Two-wire Serial Interface Characteristics” on page 313. Two different sets of specifications are presented
there, one relevant for bus speeds below 100kHz, and one valid for bus speeds up to 400kHz.
22.3 Data Transfer and Frame Format
22.3.1 Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line
must be stable when the clock line is high. The only exception to this rule is for generating start and stop
conditions.
Figure 22-2. Data Validity
Table 22-1. TWI Terminology
Term Description
Master
The device that initiates and terminates a transmission. The Master also generates the
SCL clock.
Slave The device addressed by a Master.
Transmitter The device placing data on the bus.
Receiver The device reading data from the bus.
SDA
SCL
Data Stable Data Stable
Data Change