Data Sheet

169
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
19.5.2 SPSR – SPI Status Register
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and
global interrupts are enabled. If SS
is an input and is driven low when the SPI is in Master mode, this will also
set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the
SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the
SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data
Register.
• Bit [5:1] – Reserved
These bits are reserved bits in the ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master
mode (see Table 19-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI
is configured as Slave, the SPI is only guaranteed to work at f
osc
/4 or lower.
The SPI interface on the ATmega48A/PA/88A/PA/168A/PA/328/P is also used for program memory and
EEPROM downloading or uploading. See page 295 for serial programming and verification.
Table 19-5. Relationship Between SCK and the Oscillator Frequency
SPI2X SPR1 SPR0 SCK Frequency
000
f
osc
/4
001f
osc
/16
010f
osc
/64
011
f
osc
/128
100f
osc
/2
101f
osc
/8
110
f
osc
/32
111f
osc
/64
Bit 76543210
0x2D (0x4D) SPIF WCOL – – – – – SPI2X SPSR
Read/Write RRRRRRRR/W
Initial Value 0 0 0 0 0 0 0 0