Data Sheet

151
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
18.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
T2
) is therefore
shown as a clock enable signal. In asynchronous mode, clk
I/O
should be replaced by the Timer/Counter
Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 18-8 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all
modes other than phase correct PWM mode.
Figure 18-8. Timer/Counter Timing Diagram, no Prescaling
Figure 18-9 shows the same timing data, but with the prescaler enabled.
Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 18-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f
clk_I/O
/8)
Figure 18-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)