Datasheet

18
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Figure 7-2. Data Memory Map
7.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 7-3.
Figure 7-3. On-chip Data SRAM Access Cycles
7.4 EEPROM Data Memory
The ATmega328P contains 1K byte of data EEPROM memory. It is organized as a separate
data space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register.
“Memory Programming” on page 286 contains a detailed description on EEPROM Programming
in SPI or Parallel Programming mode.
32 Registers
64 I/O Registers
Internal SRAM
(2048 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x08FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction