Datasheet
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. Resources
- 4. Data Retention
- 5. About Code Examples
- 6. Capacitive touch sensing
- 7. AVR CPU Core
- 8. AVR Memories
- 9. System Clock and Clock Options
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. Interrupts
- 13. External Interrupts
- 13.1 Pin Change Interrupt Timing
- 13.2 Register Description
- 13.2.1 EICRA – External Interrupt Control Register A
- 13.2.2 EIMSK – External Interrupt Mask Register
- 13.2.3 EIFR – External Interrupt Flag Registe
- 13.2.4 PCMSK3 – Pin Change Mask Register 3(1)
- 13.2.5 PCMSK2 – Pin Change Mask Register 2(1)
- 13.2.6 PCMSK1 – Pin Change Mask Register 1
- 13.2.7 PCMSK0 – Pin Change Mask Register 0
- 14. I/O-Ports
- 14.1 Overview
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
- 14.4.1 MCUCR – MCU Control Register
- 14.4.2 PORTA – Port A Data Register
- 14.4.3 DDRA – Port A Data Direction Register
- 14.4.4 PINA – Port A Input Pins Address
- 14.4.5 PORTB – Port B Data Register
- 14.4.6 DDRB – Port B Data Direction Register
- 14.4.7 PINB – Port B Input Pins Address
- 14.4.8 PORTC – Port C Data Register
- 14.4.9 DDRC – Port C Data Direction Register
- 14.4.10 PINC – Port C Input Pins Address
- 14.4.11 PORTD – Port D Data Register
- 14.4.12 DDRD – Port D Data Direction Register
- 14.4.13 PIND – Port D Input Pins Address
- 14.4.14 PORTE – Port E Data Register
- 14.4.15 DDRE – Port E Data Direction Register
- 14.4.16 PINE – Port E Input Pins Address
- 14.4.17 PORTF – Port F Data Register
- 14.4.18 DDRF – Port F Data Direction Register
- 14.4.19 PINF – Port F Input Pins Address
- 14.4.20 PORTG – Port G Data Register
- 14.4.21 DDRG – Port G Data Direction Register
- 14.4.22 PING – Port G Input Pins Address
- 14.4.23 PORTH – Port H Data Register(1)
- 14.4.24 DDRH – Port H Data Direction Register(1)
- 14.4.25 PINH – Port H Input Pins Address(1)
- 14.4.26 PORTJ – Port J Data Register(1)
- 14.4.27 DDRJ – Port J Data Direction Register(1)
- 14.4.28 PINJ – Port J Input Pins Address(1)
- 15. 8-bit Timer/Counter0 with PWM
- 16. Timer/Counter0 and Timer/Counter1 Prescalers
- 17. 16-bit Timer/Counter1
- 17.1 Features
- 17.2 Overview
- 17.3 Accessing 16-bit Registers
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Output Compare Units
- 17.8 Compare Match Output Unit
- 17.9 Modes of Operation
- 17.10 Timer/Counter Timing Diagrams
- 17.11 Register Description
- 17.11.1 TCCR1A – Timer/Counter1 Control Register A
- 17.11.2 TCCR1B – Timer/Counter1 Control Register B
- 17.11.3 TCCR1C – Timer/Counter1 Control Register C
- 17.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 17.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 17.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 17.11.7 ICR1H and ICR1L – Input Capture Register 1
- 17.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
- 17.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
- 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 18.1 Features
- 18.2 Overview
- 18.3 Timer/Counter Clock Sources
- 18.4 Counter Unit
- 18.5 Output Compare Unit
- 18.6 Compare Match Output Unit
- 18.7 Modes of Operation
- 18.8 Timer/Counter Timing Diagrams
- 18.9 Asynchronous Operation of Timer/Counter2
- 18.10 Timer/Counter Prescaler
- 18.11 Register Description
- 18.11.1 TCCR2A – Timer/Counter Control Register A
- 18.11.2 TCNT2 – Timer/Counter Register
- 18.11.3 OCR2A – Output Compare Register A
- 18.11.4 ASSR – Asynchronous Status Register
- 18.11.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register
- 18.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register
- 18.11.7 GTCCR – General Timer/Counter Control Register
- 19. SPI – Serial Peripheral Interface
- 20. USART0
- 20.1 Features
- 20.2 Overview
- 20.3 Clock Generation
- 20.4 Frame Formats
- 20.5 USART Initialization
- 20.6 Data Transmission – The USART Transmitter
- 20.7 Data Reception – The USART Receiver
- 20.8 Asynchronous Data Reception
- 20.9 Multi-processor Communication Mode
- 20.10 Examples of Baud Rate Setting
- 20.11 Register Description
- 21. USI – Universal Serial Interface
- 22. Analog Comparator
- 23. Analog to Digital Converter
- 24. JTAG Interface and On-chip Debug System
- 25. IEEE 1149.1 (JTAG) Boundary-scan
- 26. Boot Loader Support – Read-While-Write Self-Programming
- 26.1 Features
- 26.2 Overview
- 26.3 Application and Boot Loader Flash Sections
- 26.4 Read-While-Write and No Read-While-Write Flash Sections
- 26.5 Boot Loader Lock Bits
- 26.6 Entering the Boot Loader Program
- 26.7 Addressing the Flash During Self-Programming
- 26.8 Self-Programming the Flash
- 26.8.1 Performing Page Erase by SPM
- 26.8.2 Filling the Temporary Buffer (Page Loading)
- 26.8.3 Performing a Page Write
- 26.8.4 Using the SPM Interrupt
- 26.8.5 Consideration While Updating BLS
- 26.8.6 Prevent Reading the RWW Section During Self-Programming
- 26.8.7 Setting the Boot Loader Lock Bits by SPM
- 26.8.8 EEPROM Write Prevents Writing to SPMCSR
- 26.8.9 Reading the Fuse and Lock Bits from Software
- 26.8.10 Preventing Flash Corruption
- 26.8.11 Programming Time for Flash when Using SPM
- 26.8.12 Simple Assembly Code Example for a Boot Loader
- 26.8.13 Atmel ATmega325/3250/645/6450 Boot Loader Parameters
- 26.9 Register Description
- 27. Memory Programming
- 27.1 Program And Data Memory Lock Bits
- 27.2 Fuse Bits
- 27.3 Signature Bytes
- 27.4 Calibration Byte
- 27.5 Parallel Programming Parameters, Pin Mapping, and Commands
- 27.6 Parallel Programming
- 27.6.1 Enter Programming Mode
- 27.6.2 Considerations for Efficient Programming
- 27.6.3 Chip Erase
- 27.6.4 Programming the Flash
- 27.6.5 Programming the EEPROM
- 27.6.6 Reading the Flash
- 27.6.7 Reading the EEPROM
- 27.6.8 Programming the Fuse Low Bits
- 27.6.9 Programming the Fuse High Bits
- 27.6.10 Programming the Extended Fuse Bits
- 27.6.11 Programming the Lock Bits
- 27.6.12 Reading the Fuse and Lock Bits
- 27.6.13 Reading the Signature Bytes
- 27.6.14 Reading the Calibration Byte
- 27.6.15 Parallel Programming Characteristics
- 27.7 Serial Downloading
- 27.8 Programming via the JTAG Interface
- 27.8.1 Programming Specific JTAG Instructions
- 27.8.2 AVR_RESET (0xC)
- 27.8.3 PROG_ENABLE (0x4)
- 27.8.4 PROG_COMMANDS (0x5)
- 27.8.5 PROG_PAGELOAD (0x6)
- 27.8.6 PROG_PAGEREAD (0x7)
- 27.8.7 Data Registers
- 27.8.8 Reset Register
- 27.8.9 Programming Enable Register
- 27.8.10 Programming Command Register
- 27.8.11 Flash Data Byte Register
- 27.8.12 Programming Algorithm
- 27.8.13 Entering Programming Mode
- 27.8.14 Leaving Programming Mode
- 27.8.15 Performing Chip Erase
- 27.8.16 Programming the Flash
- 27.8.17 Reading the Flash
- 27.8.18 Programming the EEPROM
- 27.8.19 Reading the EEPROM
- 27.8.20 Programming the Fuses
- 27.8.21 Programming the Lock Bits
- 27.8.22 Reading the Fuses and Lock Bits
- 27.8.23 Reading the Signature Bytes
- 27.8.24 Reading the Calibration Byte
- 28. Electrical Characteristics
- 29. Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Supply Current of I/O modules
- 29.4 Power-down Supply Current
- 29.5 Power-save Supply Current
- 29.6 Standby Supply Current
- 29.7 Pin Pull-up
- 29.8 Pin Driver Strength
- 29.9 Pin Thresholds and hysteresis
- 29.10 BOD Thresholds and Analog Comparator Offset
- 29.11 Internal Oscillator Speed
- 29.12 Current Consumption of Peripheral Units
- 29.13 Current Consumption in Reset and Reset Pulsewidth
- 30. Register Summary
- 31. Instruction Set Summary
- 32. Ordering Information
- 33. Packaging Information
- 34. Errata
- 35. Datasheet Revision History
- 35.1 Rev. 2570N – 05/11
- 35.2 Rev. 2570M – 04/11
- 35.3 Rev. 2570L – 08/07
- 35.4 Rev. 2570K – 04/07
- 35.5 Rev. 2570J – 11/06
- 35.6 Rev. 2570I – 07/06
- 35.7 Rev. 2570H – 06/06
- 35.8 Rev. 2570G – 04/06
- 35.9 Rev. 2570F – 03/06
- 35.10 Rev. 2570E – 03/06
- 35.11 Rev. 2570D – 05/05
- 35.12 Rev. 2570C – 11/04
- 35.13 Rev. 2570B – 09/04
- 35.14 Rev. 2570A – 09/04
- Table of Contents
223
2570N–AVR–05/11
ATmega325/3250/645/6450
24.8 Using the JTAG Programming Capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG program-
ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming and verifying.
• EEPROM programming and verifying.
• Fuse programming and verifying.
• Lock bit programming and verifying.
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section “Programming via the JTAG Interface” on page 284.
24.9 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992.
24.10 Register Description
24.10.1 OCDR – On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the micro-
controller to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the
IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
Bit 7 6543210
0x31 (0x51) MSB/IDRD LSB OCDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0