Datasheet
Table Of Contents
- Features
- 1. Pin Configurations
- 2. Overview
- 3. Resources
- 4. Data Retention
- 5. About Code Examples
- 6. Capacitive touch sensing
- 7. AVR CPU Core
- 8. AVR Memories
- 9. System Clock and Clock Options
- 10. Power Management and Sleep Modes
- 11. System Control and Reset
- 12. Interrupts
- 13. External Interrupts
- 13.1 Pin Change Interrupt Timing
- 13.2 Register Description
- 13.2.1 EICRA – External Interrupt Control Register A
- 13.2.2 EIMSK – External Interrupt Mask Register
- 13.2.3 EIFR – External Interrupt Flag Registe
- 13.2.4 PCMSK3 – Pin Change Mask Register 3(1)
- 13.2.5 PCMSK2 – Pin Change Mask Register 2(1)
- 13.2.6 PCMSK1 – Pin Change Mask Register 1
- 13.2.7 PCMSK0 – Pin Change Mask Register 0
- 14. I/O-Ports
- 14.1 Overview
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
- 14.4.1 MCUCR – MCU Control Register
- 14.4.2 PORTA – Port A Data Register
- 14.4.3 DDRA – Port A Data Direction Register
- 14.4.4 PINA – Port A Input Pins Address
- 14.4.5 PORTB – Port B Data Register
- 14.4.6 DDRB – Port B Data Direction Register
- 14.4.7 PINB – Port B Input Pins Address
- 14.4.8 PORTC – Port C Data Register
- 14.4.9 DDRC – Port C Data Direction Register
- 14.4.10 PINC – Port C Input Pins Address
- 14.4.11 PORTD – Port D Data Register
- 14.4.12 DDRD – Port D Data Direction Register
- 14.4.13 PIND – Port D Input Pins Address
- 14.4.14 PORTE – Port E Data Register
- 14.4.15 DDRE – Port E Data Direction Register
- 14.4.16 PINE – Port E Input Pins Address
- 14.4.17 PORTF – Port F Data Register
- 14.4.18 DDRF – Port F Data Direction Register
- 14.4.19 PINF – Port F Input Pins Address
- 14.4.20 PORTG – Port G Data Register
- 14.4.21 DDRG – Port G Data Direction Register
- 14.4.22 PING – Port G Input Pins Address
- 14.4.23 PORTH – Port H Data Register(1)
- 14.4.24 DDRH – Port H Data Direction Register(1)
- 14.4.25 PINH – Port H Input Pins Address(1)
- 14.4.26 PORTJ – Port J Data Register(1)
- 14.4.27 DDRJ – Port J Data Direction Register(1)
- 14.4.28 PINJ – Port J Input Pins Address(1)
- 15. 8-bit Timer/Counter0 with PWM
- 16. Timer/Counter0 and Timer/Counter1 Prescalers
- 17. 16-bit Timer/Counter1
- 17.1 Features
- 17.2 Overview
- 17.3 Accessing 16-bit Registers
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Output Compare Units
- 17.8 Compare Match Output Unit
- 17.9 Modes of Operation
- 17.10 Timer/Counter Timing Diagrams
- 17.11 Register Description
- 17.11.1 TCCR1A – Timer/Counter1 Control Register A
- 17.11.2 TCCR1B – Timer/Counter1 Control Register B
- 17.11.3 TCCR1C – Timer/Counter1 Control Register C
- 17.11.4 TCNT1H and TCNT1L – Timer/Counter1
- 17.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
- 17.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B
- 17.11.7 ICR1H and ICR1L – Input Capture Register 1
- 17.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
- 17.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
- 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 18.1 Features
- 18.2 Overview
- 18.3 Timer/Counter Clock Sources
- 18.4 Counter Unit
- 18.5 Output Compare Unit
- 18.6 Compare Match Output Unit
- 18.7 Modes of Operation
- 18.8 Timer/Counter Timing Diagrams
- 18.9 Asynchronous Operation of Timer/Counter2
- 18.10 Timer/Counter Prescaler
- 18.11 Register Description
- 18.11.1 TCCR2A – Timer/Counter Control Register A
- 18.11.2 TCNT2 – Timer/Counter Register
- 18.11.3 OCR2A – Output Compare Register A
- 18.11.4 ASSR – Asynchronous Status Register
- 18.11.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register
- 18.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register
- 18.11.7 GTCCR – General Timer/Counter Control Register
- 19. SPI – Serial Peripheral Interface
- 20. USART0
- 20.1 Features
- 20.2 Overview
- 20.3 Clock Generation
- 20.4 Frame Formats
- 20.5 USART Initialization
- 20.6 Data Transmission – The USART Transmitter
- 20.7 Data Reception – The USART Receiver
- 20.8 Asynchronous Data Reception
- 20.9 Multi-processor Communication Mode
- 20.10 Examples of Baud Rate Setting
- 20.11 Register Description
- 21. USI – Universal Serial Interface
- 22. Analog Comparator
- 23. Analog to Digital Converter
- 24. JTAG Interface and On-chip Debug System
- 25. IEEE 1149.1 (JTAG) Boundary-scan
- 26. Boot Loader Support – Read-While-Write Self-Programming
- 26.1 Features
- 26.2 Overview
- 26.3 Application and Boot Loader Flash Sections
- 26.4 Read-While-Write and No Read-While-Write Flash Sections
- 26.5 Boot Loader Lock Bits
- 26.6 Entering the Boot Loader Program
- 26.7 Addressing the Flash During Self-Programming
- 26.8 Self-Programming the Flash
- 26.8.1 Performing Page Erase by SPM
- 26.8.2 Filling the Temporary Buffer (Page Loading)
- 26.8.3 Performing a Page Write
- 26.8.4 Using the SPM Interrupt
- 26.8.5 Consideration While Updating BLS
- 26.8.6 Prevent Reading the RWW Section During Self-Programming
- 26.8.7 Setting the Boot Loader Lock Bits by SPM
- 26.8.8 EEPROM Write Prevents Writing to SPMCSR
- 26.8.9 Reading the Fuse and Lock Bits from Software
- 26.8.10 Preventing Flash Corruption
- 26.8.11 Programming Time for Flash when Using SPM
- 26.8.12 Simple Assembly Code Example for a Boot Loader
- 26.8.13 Atmel ATmega325/3250/645/6450 Boot Loader Parameters
- 26.9 Register Description
- 27. Memory Programming
- 27.1 Program And Data Memory Lock Bits
- 27.2 Fuse Bits
- 27.3 Signature Bytes
- 27.4 Calibration Byte
- 27.5 Parallel Programming Parameters, Pin Mapping, and Commands
- 27.6 Parallel Programming
- 27.6.1 Enter Programming Mode
- 27.6.2 Considerations for Efficient Programming
- 27.6.3 Chip Erase
- 27.6.4 Programming the Flash
- 27.6.5 Programming the EEPROM
- 27.6.6 Reading the Flash
- 27.6.7 Reading the EEPROM
- 27.6.8 Programming the Fuse Low Bits
- 27.6.9 Programming the Fuse High Bits
- 27.6.10 Programming the Extended Fuse Bits
- 27.6.11 Programming the Lock Bits
- 27.6.12 Reading the Fuse and Lock Bits
- 27.6.13 Reading the Signature Bytes
- 27.6.14 Reading the Calibration Byte
- 27.6.15 Parallel Programming Characteristics
- 27.7 Serial Downloading
- 27.8 Programming via the JTAG Interface
- 27.8.1 Programming Specific JTAG Instructions
- 27.8.2 AVR_RESET (0xC)
- 27.8.3 PROG_ENABLE (0x4)
- 27.8.4 PROG_COMMANDS (0x5)
- 27.8.5 PROG_PAGELOAD (0x6)
- 27.8.6 PROG_PAGEREAD (0x7)
- 27.8.7 Data Registers
- 27.8.8 Reset Register
- 27.8.9 Programming Enable Register
- 27.8.10 Programming Command Register
- 27.8.11 Flash Data Byte Register
- 27.8.12 Programming Algorithm
- 27.8.13 Entering Programming Mode
- 27.8.14 Leaving Programming Mode
- 27.8.15 Performing Chip Erase
- 27.8.16 Programming the Flash
- 27.8.17 Reading the Flash
- 27.8.18 Programming the EEPROM
- 27.8.19 Reading the EEPROM
- 27.8.20 Programming the Fuses
- 27.8.21 Programming the Lock Bits
- 27.8.22 Reading the Fuses and Lock Bits
- 27.8.23 Reading the Signature Bytes
- 27.8.24 Reading the Calibration Byte
- 28. Electrical Characteristics
- 29. Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Supply Current of I/O modules
- 29.4 Power-down Supply Current
- 29.5 Power-save Supply Current
- 29.6 Standby Supply Current
- 29.7 Pin Pull-up
- 29.8 Pin Driver Strength
- 29.9 Pin Thresholds and hysteresis
- 29.10 BOD Thresholds and Analog Comparator Offset
- 29.11 Internal Oscillator Speed
- 29.12 Current Consumption of Peripheral Units
- 29.13 Current Consumption in Reset and Reset Pulsewidth
- 30. Register Summary
- 31. Instruction Set Summary
- 32. Ordering Information
- 33. Packaging Information
- 34. Errata
- 35. Datasheet Revision History
- 35.1 Rev. 2570N – 05/11
- 35.2 Rev. 2570M – 04/11
- 35.3 Rev. 2570L – 08/07
- 35.4 Rev. 2570K – 04/07
- 35.5 Rev. 2570J – 11/06
- 35.6 Rev. 2570I – 07/06
- 35.7 Rev. 2570H – 06/06
- 35.8 Rev. 2570G – 04/06
- 35.9 Rev. 2570F – 03/06
- 35.10 Rev. 2570E – 03/06
- 35.11 Rev. 2570D – 05/05
- 35.12 Rev. 2570C – 11/04
- 35.13 Rev. 2570B – 09/04
- 35.14 Rev. 2570A – 09/04
- Table of Contents
117
2570N–AVR–05/11
ATmega325/3250/645/6450
to be written anytime. When the OCR1A I/O location is written the value written will be put into
the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done
at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM1x1:0 to three (see Table 17-3 on page 124). The actual
OC1x value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out-
put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of f
OC
1
A
= f
clk_I/O
/2 when OCR1A is set to zero (0x0000). This feature is
similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Com-
pare unit is enabled in the fast PWM mode.
17.9.4 Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual-
slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while counting up, and set on the
compare match while counting down. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
f
OCnxPWM
f
clk_I/O
N 1 TOP+()⋅
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