Datasheet

99
8023F–AVR–07/09
ATmega325P/3250P
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the way
up.
14.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 4 contains timing data for basic Timer/Counter operation. The figure shows
the count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 4. Timer/Counter Timing Diagram, no Prescaling
Figure 5 shows the same timing data, but with the prescaler enabled.
Figure 5. Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
Figure 6 shows the setting of OCF0A in all modes except CTC mode.
Figure 6. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f
clk_I/O
/8)
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn
MAX - 1 MAX BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)