Datasheet

35
8023F–AVR–07/09
ATmega325P/3250P
one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the
MCU is kept in Reset during such changes in the clock frequency.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page
35 for details.
8.8 Clock Output Buffer
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when the chip clock is used to drive other circuits on the system. The clock will be out-
put also during reset and the normal operation of I/O pin will be overridden when the fuse is
programmed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output when the CKOUT Fuse is programmed.
8.9 Timer/Counter Oscillator
ATmega325P/3250P uses the same crystal oscillator for Low-frequency Oscillator and
Timer/Counter Oscillator. See ”Low-frequency Crystal Oscillator” on page 32 for details on the
oscillator and crystal requirements.
ATmega325P/3250P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1
and XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times
the oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only
be used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See ”Timer/Counter Timing Diagram, Clear Timer on Compare Match mode,
with Prescaler (fclk_I/O/8)” on page 146 for further description on selecting external clock as
input instead of a 32.768 kHz watch crystal.
8.10 System Clock Prescaler
The ATmega325P/3250P system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clk
I/O
, clk
ADC
, clk
CPU
, and clk
FLASH
are divided by a factor as shown in Table 8-10.
8.10.1 Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the
new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the
previous clock period, and T2 is the period corresponding to the new prescaler setting.