Datasheet

154
8023F–AVR–07/09
ATmega325P/3250P
17. SPI – Serial Peripheral Interface
17.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
17.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega325P/3250P and peripheral devices or between several AVR devices. A simplified block
diagram of the Serial Peripheral Interface is shown in Figure 17-1.
The PRSPI bit in ”PRR – Power Reduction Register” on page 44 must be written to zero to
enable the SPI module.
Figure 17-1. SPI Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 2, and Table 13-3 on page 71 for SPI pin placement.
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128