Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 32K Bytes of In-System Self-programmable Flash program memory – 1K Bytes EEPROM – 2K Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEP
1. Pin Configurations Figure 1-1.
ATmega325P/3250P DNC 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 PA1 PA2 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega325P 64 Figure 1-2.
Block Diagram GND Block Diagram PF0 - PF7 VCC PORTA DRIVERS PORTF DRIVERS DATA DIR. REG. PORTF DATA REGISTER PORTF PC0 - PC7 PA0 - PA7 PORTC DRIVERS DATA DIR. REG. PORTA DATA REGISTER PORTA XTAL2 Figure 2-1. XTAL1 2.1 DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND CALIB.
ATmega325P/3250P The ATmega325P/3250P provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channe
2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated.
ATmega325P/3250P resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega325P/3250P as listed on page 75. 2.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit).
2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset Characterizations” on page 308. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.
ATmega325P/3250P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.
Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation.
ATmega325P/3250P 6. AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1.
ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
ATmega325P/3250P 6.4 AVR Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
• Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega325P/3250P 6.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure .
6.6.1 SPH and SPL – Stack Pointer High and Stack Pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 6.
ATmega325P/3250P 6.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
ATmega325P/3250P 7. AVR Memories 7.1 Overview This section describes the different memories in the ATmega325P/3250P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega325P/3250P features an EEPROM Memory for data storage. All three memory spaces are linear. 7.2 In-System Reprogrammable Flash Program Memory The ATmega325P/3250P contains 32K bytes On-chip In-System Reprogrammable Flash memory for program storage.
Figure 7-1. Program Memory Map Program Memory 0x0000 Application Flash Section Boot Flash Section 0x3FFF 7.3 SRAM Data Memory Figure 7-2 shows how the ATmega325P/3250P SRAM Memory is organized. The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega325P/3250P these addressing modes. The Register File is described in ”General Purpose Register File” on page 14. Figure 7-2. Data Memory Map Data Memory 32 Registers 64 I/O Registers 160 Ext I/O Reg. 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF 0x0100 Internal SRAM (2048 x 8) 0x08FF 7.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 7-3.
The write access time for the EEPROM is given in Table 7-1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section “7.4.3” on page 22.
ATmega325P/3250P reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them.
7.6.3 EECR – The EEPROM Control Register Bit 7 6 5 4 3 2 1 0 0x1F (0x3F) – – – – EERIE EEMWE EEWE EERE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 EECR • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt.
ATmega325P/3250P When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read.
Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to Data Register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega325P/3250P Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
7.6.
ATmega325P/3250P 8. System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power Management and Sleep Modes” on page 38. The clock systems are detailed below. Figure 8-1.
8.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 8.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
ATmega325P/3250P 8.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
Table 8-4. CKSEL0 Start-up Time from Power-down and Power-save SUT1..0 (2) Additional Delay from Reset (VCC = 5.0V) Recommended Usage 0 11 1K CK 14CK + 4.1 ms Ceramic resonator, fast rising power 1 00 1K CK(2) 14CK + 65 ms Ceramic resonator, slowly rising power 01 16K CK 14CK Crystal Oscillator, BOD enabled 10 16K CK 14CK + 4.1 ms Crystal Oscillator, fast rising power 11 16K CK 14CK + 65 ms Crystal Oscillator, slowly rising power 1 1 1 Notes: 8.
ATmega325P/3250P The Low-frequency Crystal Oscillator must be selected by setting the CKSEL Fuses to “0110” or “0111” as shown in Table 8-7. Start-up times are determined by the SUT Fuses as shown in Table 8-6. Table 8-6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1..0 Additional Delay from Reset (VCC = 5.0V) 00 4 CK 01 4 CK + 4.1 ms Slowly rising power 10 4 CK + 65 ms Stable frequency at start-up 11 CKSEL3..
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 8-9 on page 34. Table 8-9. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) SUT1..0 BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms(1) 10 Power Conditions Reserved Note: 8.7 11 1. The device is shipped with this option selected.
ATmega325P/3250P one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page 35 for details. 8.8 Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO.
8.11 8.11.1 Register Description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
ATmega325P/3250P To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits.
ATmega325P/3250P 9. Power Management and Sleep Modes 9.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
9.3 BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 25-3 on page 272, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page 38. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode.
ATmega325P/3250P 9.6 Power-down Mode When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU.
9.10 Minimizing Power Consumption There are several possibilities to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 9.10.
ATmega325P/3250P some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 67 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times.
9.11 9.11.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 9-2. Table 9-2.
ATmega325P/3250P The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 9.11.
ATmega325P/3250P 10. System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 10-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characterizations” on page 308.
ATmega325P/3250P Figure 10-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characterizations” on page 308) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 10-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 10.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 49 for details on operation of the Watchdog Timer. Figure 10-6. Watchdog Reset During Operation CC CK 10.
ATmega325P/3250P ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 10.4 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels.
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. 10.4.3 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period.
ATmega325P/3250P 10.5.2 WDTCR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) – – – WDCE WDE WDP2 WDP1 WDP0 Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WDTCR • Bits 7:5 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled.
The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
ATmega325P/3250P 11. Interrupts 11.1 Overview This section describes the specifics of the interrupt handling as performed in ATmega325P/3250P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 17. 11.2 Interrupt Vectors Table 11-1. Reset and Interrupt Vectors Vector No.
2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 3. PCINT2 and PCINT3 are only present in ATmega3250P and ATmega6450P. Table 11-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings.
ATmega325P/3250P 0x0032 ldi r16, high(RAMEND) ; Main program start 0x0033 RESET: out SPH,r16 ; Set Stack Pointer to top of RAM 0x0034 ldi r16, low(RAMEND) 0x0035 out SPL,r16 0x0036 sei 0x0037 xxx ... ... ...
Address Labels Code Comments ; .org 0x3800/0x7800 0x3800/0x7800 jmp 0x3802/0x7802 jmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler 0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 11.2.
ATmega325P/3250P • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below.
ATmega325P/3250P 12. External Interrupts 12.1 Overview The External Interrupts are triggered by the INT0 pin or any of the PCINT30:0 pins(2). Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15:8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles.
12.2 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 12-1. Figure 12-1. Pin Change Interrupt pin_lat PCINT(0) D pcint_in_(0) Q 0 pcint_setflag pcint_syn PCIF pin_sync LE x clk PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 12.3 12.3.
ATmega325P/3250P Table 12-1. 12.3.2 Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.
12.3.3 EIFR – External Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 PCIF3 PCIF2 PCIF1 PCIF0 – – – INTF0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1C (0x3C) EIFR • Bit 7 – PCIF3: Pin Change Interrupt Flag 3 When a logic change on any PCINT30:24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
ATmega325P/3250P 12.3.4 PCMSK3 – Pin Change Mask Register 3(1) Bit 7 6 5 4 3 2 1 0 (0x73) – PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PCMSK3 • Bit 6:0 – PCINT30:24: Pin Change Enable Mask 30:24 Each PCINT30:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin.
ATmega325P/3250P 13. I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
Functions” on page 69. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2.
ATmega325P/3250P be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 13.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Figure 13-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low.
ATmega325P/3250P Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
13.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
ATmega325P/3250P 13.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. Figure 13-5.
Table 13-2. Signal Name Generic Description of Overriding Signals for Alternate Functions Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
ATmega325P/3250P 13.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-3. Table 13-3. Port Pin Port B Pins Alternate Functions Alternate Functions PB7 OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt15). PB6 OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt14). PB5 OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt13).
PCINT12, Pin Change Interrupt Source 12: The PB4 pin can serve as an external interrupt source. • MISO/PCINT11 – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.
ATmega325P/3250P Table 13-4 and Table 13-5 relate the alternate functions of Port B to the overriding signals shown in Figure 13-5 on page 69. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 13-4.
13.3.2 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-6. Table 13-6. Port Pin Port D Pins Alternate Functions (SEG refers to 100-pin/64-pin pinout) Alternate Function PD7 PD6 PD5 PD4 PD3 PD2 PD1 INT0 (External Interrupt0 Input) PD0 ICP1 (Timer/Counter1 Input Capture pin) The alternate pin configuration is as follows: • INT0 – Port D, Bit 1 INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU.
ATmega325P/3250P 13.3.3 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-8. Table 13-8.
• XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART0 External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART0 operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source. • TXD/PCINT1 – Port E, Bit 1 TXD0, UART0 Transmit pin.
ATmega325P/3250P Table 13-10.
• TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
ATmega325P/3250P Table 13-13. Overriding Signals for Alternate Functions in PF3:PF0 13.3.5 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-14.
Table 13-15. Overriding Signals for Alternate Functions in PG4 and PG3 13.3.6 Signal Name PG4/T0 PG3/T1 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV 0 0 DI T0 INPUT T1 INPUT AIO – – Alternate Functions of Port H Port H is only present in ATmega3250P. The alternate pin configuration is as follows: Table 13-16.
ATmega325P/3250P • PCINT20 – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. • PCINT19– Port H, Bit 3 PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as an external interrupt source. • PCINT18 – Port H, Bit 2 PCINT18, Pin Change Interrupt Source 18: The PH2 pin can serve as an external interrupt source. • PCINT17/SEG – Port H, Bit 1 PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source.
Table 13-18. Overriding Signals for Alternate Functions in PH3:0 13.3.7 Signal Name PH3/PCINT19 PH2/PCINT18 PH1/PCINT17 PH0/PCINT16 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE PCINT19 • PCIE0 PCINT18 • PCIE0 PCINT17 • PCIE0 PCINT16 • PCIE0 DIEOV 0 0 0 0 DI PCINT19 INPUT PCINT18 INPUT PCINT17 INPUT PCINT16 INPUT AIO – – – – Alternate Functions of Port J Port J is only present in ATmega3250P.
ATmega325P/3250P • PCINT27 – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. • PCINT26 – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source. • PCINT25 – Port J, Bit 1 PCINT25, Pin Change Interrupt Source 25: The PE25 pin can serve as an external interrupt source. • PCINT24 – Port J, Bit 0 PCINT24, Pin Change Interrupt Source 24: The PE24 pin can serve as an external interrupt source.
Table 13-21.
ATmega325P/3250P 13.4 13.4.1 Register Description MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
13.4.8 PORTC – Port C Data Register Bit 13.4.9 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 13.4.
ATmega325P/3250P 13.4.16 PINE – Port E Input Pins Address Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 0x0C (0x2C) 13.4.17 PORTF – Port F Data Register Bit 13.4.
13.4.24 DDRH – Port H Data Direction Register(1) Bit 7 6 5 4 3 2 1 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xD9) 13.4.25 PINH – Port H Input Pins Address(1) Bit 7 6 5 4 3 2 1 0 PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A (0xD8) 13.4.26 13.4.27 13.4.
ATmega325P/3250P 14. 8-bit Timer/Counter0 with PWM 14.1 Features • • • • • • • 14.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module.
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC0A). See Section “14.5” on page 92. for details. The compare match event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 14.2.
ATmega325P/3250P clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
14.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed.
ATmega325P/3250P 14.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled). 14.5.
Figure 14-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega325P/3250P 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = -------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 14.7.
ATmega325P/3250P In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 14-4 on page 103). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 14-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATmega325P/3250P symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 14.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures.
Figure 7 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 7. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 14.9 Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings.
ATmega325P/3250P The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 14-8. T1/T0 Pin Sampling D Tn Q D Q D Tn_sync (To Clock Select Logic) Q LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated.
14.10 Register Description 14.10.1 TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode.
ATmega325P/3250P When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 14-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 14-3. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected.
• Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 14-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge.
ATmega325P/3250P • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the ”TIFR0 – Timer/Counter 0 Interrupt Flag Register” on page 105.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.
ATmega325P/3250P 15. 16-bit Timer/Counter1 15.1 Features • • • • • • • • • • • 15.2 True 16-bit Design (i.e.
Figure 15-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 15.2.1 TCCRnB 1. Refer to Figure 1-1 on page 2, Table 13.3.
ATmega325P/3250P tion “15.7” on page 116.. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
15.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
ATmega325P/3250P the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega325P/3250P 15.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
ATmega325P/3250P tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to ”Accessing 16-bit Registers” on page 110. 15.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega325P/3250P prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 15-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to “0”.
ATmega325P/3250P A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 15.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits.
Figure 15-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega325P/3250P The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega325P/3250P 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega325P/3250P the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
ATmega325P/3250P Figure 15-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 15.11 Register Description 15.11.
ATmega325P/3250P Table 15-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 15-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
Figure 15-14.
ATmega325P/3250P When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 15.11.
ATmega325P/3250P 15.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 7 6 5 4 3 (0x87) ICR1[15:8] (0x86) ICR1[7:0] 2 1 0 ICR1H ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.
ATmega325P/3250P 16. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 16.1 Features • • • • • • • 16.
16.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section.
ATmega325P/3250P 16.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surrounding environment. Figure 16-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page 140). Figure 16-3 shows a block diagram of the Output Compare unit. Figure 16-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes.
ATmega325P/3250P 16.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation.
The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is visible on the pin. The port override function is independent of the Waveform Generation mode.
ATmega325P/3250P 16.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.
16.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A, and set at BOTTOM.
ATmega325P/3250P The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = -----------------N ⋅ 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
Figure 16-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
ATmega325P/3250P symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 16.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal.
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 16-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 16-11.
ATmega325P/3250P 16.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3.
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
ATmega325P/3250P then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. If applying an external clock on TOSC1, the EXCLK bit in ASSR must be set. For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S /32, clk T2S /64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
• Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting.
ATmega325P/3250P • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 16-6. Table 16-6. 16.10.2 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
• Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero.
ATmega325P/3250P • Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 16.10.
ATmega325P/3250P 17. SPI – Serial Peripheral Interface 17.1 Features • • • • • • • • 17.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 17-2 on page 155. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega325P/3250P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 17-1. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 69. Table 17-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega325P/3250P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
17.3 17.3.1 SS Pin Functionality Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
ATmega325P/3250P Figure 17-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 17-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 17.5 17.5.
• Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero.
ATmega325P/3250P Table 17-4. 17.5.2 Relationship Between SCK and the Oscillator Frequency (Continued) SPI2X SPR1 SPR0 1 0 0 1 0 1 1 1 0 1 1 1 SCK Frequency fosc/2 fosc/8 fosc/32 fosc/64 SPSR – SPI Status Register Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x2D (0x4D) SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set.
ATmega325P/3250P 18. USART0 18.1 Features • • • • • • • • • • • • 18.
Figure 18-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER UCSRB RxD UCSRC 1. Refer to Figure 1-1 on page 2, Figure 1-2 on page 3, ”Alternate Functions of Port E” on page 75 for USART pin placement.
ATmega325P/3250P • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer.
xcki operation. 18.3.1 Input from XCK pin (internal Signal). Used for synchronous slave xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 18-2 on page 165.
ATmega325P/3250P Figure 18-3.
18.3.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 18-4. Synchronous Mode XCK Timing.
ATmega325P/3250P St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRR0H, r17 out UBRR0L, r16 ; Enable receiver and transmitter ldi r16, (1<
ATmega325P/3250P 18.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions.
18.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16.
ATmega325P/3250P contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn.
bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSR0A, RXC0 rjmp USART_Receive ; Get and return received data from buffer in r16, UDR0 ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSR0A & (1<
ATmega325P/3250P The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
18.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega325P/3250P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 18.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate.
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Figure 18-6.
ATmega325P/3250P Figure 18-8. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
Table 18-1. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 18-2.
ATmega325P/3250P nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
18.10 Register Description 18.10.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXBn[7:0] UDRn (Read) TXBn[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDRn Register location.
ATmega325P/3250P • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
ATmega325P/3250P • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Figure 18-10.
Figure 18-13. UCPOLn Bit Settings Transmitted Data Changed (Output of TxD Pin) Received Data Sampled (Input on RxD Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge UCPOLn 18.10.
ATmega325P/3250P Table 18-3. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies fosc = 1.0000 MHz Baud Rate (bps) U2Xn = 0 UBRRn fosc = 1.8432 MHz U2Xn = 1 Error UBRRn U2Xn = 0 Error UBRRn fosc = 2.0000 MHz U2Xn = 1 Error U2Xn = 0 UBRRn Error UBRRn U2Xn = 1 Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.
Table 18-4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.
ATmega325P/3250P Table 4. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz Baud Rate (bps) U2Xn = 0 U2Xn = 1 U2Xn = 0 fosc = 14.7456 MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.
Table 5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz Baud Rate (bps) U2Xn = 0 fosc = 18.4320 MHz U2Xn = 1 U2Xn = 0 fosc = 20.0000 MHz U2Xn = 1 U2Xn = 0 U2Xn = 1 UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.
ATmega325P/3250P 19. USI – Universal Serial Interface 19.1 Features • • • • • • 19.2 Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wake up from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability Overview The Universal Serial Interface, USI, provides the basic hardware resources needed for serial communication.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits.
ATmega325P/3250P Figure 19-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 19-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register. The second and third instructions clears the USI Counter Overflow Flag and the USI counter value.
ATmega325P/3250P 19.3.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
19.3.4 Two-wire Mode The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA. Figure 19-4.
ATmega325P/3250P Figure 19-5. Two-wire Mode, Typical Timing Diagram SDA SCL S A B 1-7 8 9 1-8 9 1-8 9 ADDRESS R/W ACK DATA ACK DATA ACK C D E P F Referring to the timing diagram (Figure 19-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A).
19.3.5 Start Condition Detector The start condition detector is shown in Figure 19-6 The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in Two-wire mode. The start condition detector is working asynchronously and can therefore wake up the processor from the Power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time.
ATmega325P/3250P 19.5 19.5.1 Register Descriptions USIDR – USI Data Register Bit 7 6 5 4 3 2 1 0 (0xBA) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 USIDR The USI uses no buffering of the Serial Register, i.e., when accessing the Data Register (USIDR) the Serial Register is accessed directly. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
• Bit 5 – USIPF: Stop Condition Flag When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag. This signal is useful when implementing Two-wire bus master arbitration. • Bit 4 – USIDC: Data Output Collision This bit is logical one when bit 7 in the Shift Register differs from the physical pin value. The flag is only valid when Two-wire mode is used.
ATmega325P/3250P Table 19-1. Relations between USIWM1:0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
Table 19-2 shows the relationship between the USICS1:0 and USICLK setting and clock source used for the Shift Register and the 4-bit counter. Table 19-2.
ATmega325P/3250P 20. Analog Comparator 20.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 20-1. 20.3 20.3.
ATmega325P/3250P • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
21. Analog to Digital Converter 21.1 Features • • • • • • • • • • • • • 21.2 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock) Up to 76.9 kSPS at Maximum Resolution (200 kHz ADC clock) Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
ATmega325P/3250P Figure 21-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega325P/3250P If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 21.5 Prescaling and Conversion Timing Figure 21-3.
with Auto triggering from a source other than the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 21-1. Figure 21-4.
ATmega325P/3250P Figure 21-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 21-1. MUX and REFS Update ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 21.
21.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega325P/3250P 21.7.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 21-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
Figure 21-9. ADC Power Connections VCC GND 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 10μΗ GND AVCC 100nF Analog Ground Plane 21.7.3 51 63 64 1 DNC PA0 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
ATmega325P/3250P • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 21-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB.
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
ATmega325P/3250P Figure 21-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 21-2. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 510 0x1FE 510 VADCm + /512 VREF Corresponding Decimal Value ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
21.9 21.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 6.
ATmega325P/3250P Table 21-3.
21.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega325P/3250P Table 21-4. 21.9.3 21.9.3.1 ADPS2 ADPS1 ADPS0 Division Factor 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ADCL and ADCH – The ADC Data Register ADLAR = 0 Bit 15 14 13 12 11 10 9 8 (0x79) – – – – – – ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write Initial Value 21.9.3.
21.9.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – Res: Reserved Bit This bit is reserved for future use. To ensure compatibility with future devices, this bit must be written to zero when ADCSRB is written.
ATmega325P/3250P 22. JTAG Interface and On-chip Debug System 22.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset.
ATmega325P/3250P Figure 22-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 22.
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega325P/3250P A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 227. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.
ATmega325P/3250P 23. IEEE 1149.1 (JTAG) Boundary-scan 23.1 Features • • • • • 23.2 JTAG (IEEE std. 1149.
23.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 23.3.2 Device Identification Register Figure 23-1 shows the structure of the Device Identification Register. Table 23-1.
ATmega325P/3250P Figure 23-1. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 23.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 232 for a complete description. 23.
The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 23.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register.
ATmega325P/3250P Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 23-3 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digital logic and the analog circuitry. Figure 23-2.
Figure 23-3. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR WDx RESET OCxn DATA BUS RDx Pxn 1 Q ODxn IDxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 23.5.
ATmega325P/3250P 23.5.3 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 23-5 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
23.5.4 Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 23-6. The Boundary-scan cell from Figure 23-7 is attached to each of these signals. The signals are described in Table 23-3. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 23-6. Analog Comparator BANDGAP REFERENCE ACBG ACD ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 23-7.
ATmega325P/3250P Table 23-3. 23.5.
Table 23-4.
ATmega325P/3250P Table 23-4.
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: The upper limit is: 1024 ⋅ 1,5V ⋅ 0,95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1,5V ⋅ 1,05 ⁄ 5V = 323 = 0x143 The recommended values from Table 23-4 are used unless other values are given in the algorithm in Table 23-5.
ATmega325P/3250P 23.6 ATmega325P/3250P Boundary-scan Order Table 23-6 and Table 23-7 shows the Scan order between TDI and TDO when the Boundaryscan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
Table 23-6.
ATmega325P/3250P Table 23-6. ATmega325P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 157 PE0.Data 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.Control 137 PE6.
Table 23-6. ATmega325P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 133 PB0.Data 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.Control 113 PB6.
ATmega325P/3250P Table 23-6. ATmega325P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 100 EXTCLKEN 99 OSCON 98 RCOSCEN 97 OSC32EN 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pull-up_Enable 77 PD5.Data 76 PD5.
Table 23-6. ATmega325P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 64 PG1.Control 63 PG1.Pull-up_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.Control 42 PC6.
ATmega325P/3250P Table 23-6. ATmega325P Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.
Table 23-7.
ATmega325P/3250P Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.Data 186 PE5.Control 185 PE5.
Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.Control 152 PB6.Pull-up_Enable 151 PB7.
ATmega325P/3250P Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 135 EXTCLK (XTAL1) 134 OSCCK 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.Control 117 PJ6.Pull-up_Enable 116 PD0.Data 115 PD0.Control 114 PD0.
Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.Data 79 PC2.Control 78 PC2.Pull-up_Enable 77 PC3.
ATmega325P/3250P Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.Data 43 PA6.Control 42 PA6.
Table 23-7. ATmega3250P Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pull-up_Enable 5 PF1.
ATmega325P/3250P 23.8 23.8.1 Register Description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS BODSE PUD – – IVSEL IVCE Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled.
ATmega325P/3250P 24. Boot Loader Support – Read-While-Write Self-Programming 24.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 24.2 1. A page is a section in the Flash consisting of several bytes (see Table 25-11 on page 276) used during programming.
24.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega325P/3250P Figure 24-1. Read-While-Write vs.
Figure 24-2.
ATmega325P/3250P Table 24-2. Boot Lock Bit0 Protection Modes (Application Section)(1) BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section.
24.6 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the application code is loaded, the program can start executing the application code.
ATmega325P/3250P Figure 24-3. Addressing the Flash During SPM(1) BIT 15 ZPCMSB ZPAGEMSB Z - REGISTER 1 0 0 PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE WORD ADDRESS WITHIN A PAGE PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02 PAGEEND Notes: 24.8 1. The different variables used in Figure 24-3 on page 262 are listed in Table 24-8 on page 268. 2. PCPAGE and PCWORD are listed in Table 25-11 on page 276.
24.8.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase. • Page Erase to the NRWW section: The CPU is halted during the operation.
ATmega325P/3250P RWWSB by writing the RWWSRE. See ”Simple Assembly Code Example for a Boot Loader” on page 266 for an example. 24.8.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits and general Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Bit 7 6 5 4 3 2 1 0 Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 25-3 on page 272 for detailed description and mapping of the Extended Fuse byte.
ATmega325P/3250P 24.8.12 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
ATmega325P/3250P 24.8.13 ATmega325P/3250P Boot Loader Parameters In Table 24-6 through Table 24-8, the parameters used in the description of the Self-Programming are given. Table 24-6.
24.9 24.9.1 Register Description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega325P/3250P • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
ATmega325P/3250P 25. Memory Programming 25.1 Program And Data Memory Lock Bits The ATmega325P/3250P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1.
Lock Bit Protection Modes(1)(2) (Continued) Table 25-2. Memory Lock Bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega325P/3250P Table 25-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
25.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
ATmega325P/3250P Figure 25-1. Parallel Programming +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V BS2 VCC +5V AVCC PB7 - PB0 DATA RESET PA0 XTAL1 GND Table 25-7. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low).
Table 25-9. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 25-10.
ATmega325P/3250P 5. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 6. Wait at least 300 µs before giving any parallel programming commands. 7. Exit Programming mode by power the device down or by bringing RESET pin to 0V. If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used. 1.
A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to “01”.
ATmega325P/3250P 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 25-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1.
25.6.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 276. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to ”Programming the Flash” on page 277 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
ATmega325P/3250P 25.6.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to ”Programming the Flash” on page 277 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 25.6.
Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte DATA A C 0x40 DATA XX Write Fuse high byte A C 0x40 DATA XX Write Extended Fuse byte A C 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 25.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to ”Programming the Flash” on page 277 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte.
ATmega325P/3250P Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read 0 Fuse Low Byte 0 Extended Fuse Byte 1 DATA BS2 0 Lock Bits 1 Fuse High Byte BS1 1 BS2 25.6.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to ”Programming the Flash” on page 277 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”.
Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 25-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 25-9.
ATmega325P/3250P Table 25-13.
Figure 25-10. Serial Programming and Verify(1) +1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI AVCC MISO SCK XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.
ATmega325P/3250P Serial Programming Algorithm When writing serial data to the ATmega325P/3250P, data is clocked on the rising edge of SCK. When reading data from the ATmega325P/3250P, data is clocked on the falling edge of SCK. See Figure 25-11 for timing details. To program and verify the ATmega325P/3250P in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-16): 1.
Table 25-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5 ms tWD_FLASH 4.5 ms tWD_EEPROM 9.0 ms tWD_ERASE 9.0 ms Figure 25-11.
ATmega325P/3250P Serial Programming Instruction set Table 25-16 and Figure 25-12 on page 290 describes the Instruction set. Table 25-16.
Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts a = address Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use word address. This address may be random within the page range. 7. See htt://www.atmel.
ATmega325P/3250P 25.8 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Figure 25-13. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.8.2 1 Exit1-IR 0 1 0 Shift-IR 1 0 1 Update-IR 0 1 0 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
ATmega325P/3250P 25.8.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
25.8.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section ”Programming Specific JTAG Instructions” on page 291. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 25.8.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode.
ATmega325P/3250P Figure 25-15.
Table 25-17. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b.
ATmega325P/3250P Table 25-17. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b.
Table 25-17. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a.
ATmega325P/3250P Figure 25-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 25.8.
ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 25-17.
ATmega325P/3250P 25.8.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 25-13 on page 284). 25.8.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 301. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 25-11 on page 276) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash).
ATmega325P/3250P 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 25-13 on page 284). 25.8.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5.
ATmega325P/3250P 26. Electrical Characteristics 26.1 Absolute Maximum Ratings* Operating Temperature....................................-55⋅C to +125⋅C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40⋅C to 85⋅C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Power Supply Current ICC Power-save mode Power-down mode(5) Condition Typ. Max. Units Active 1 MHz, VCC = 2V 0.5 0.75 mA Active 4 MHz, VCC = 3V 2.6 3.5 mA Active 8 MHz, VCC = 5V 9 12 mA Idle 1 MHz, VCC = 2V 0.14 0.25 mA Idle 4 MHz, VCC = 3V 0.75 1.5 mA Idle 8 MHz, VCC = 5V 2.9 5 mA 32 kHz TOSC enabled, VCC = 1.8V 0.
ATmega325P/3250P 26.3 Speed Grades Figure 26-1. Maximum Frequency vs. VCC (4 - 10 MHz). 10 MHz Safe Operating Area 4 MHz 1.8V 2.7V 5.5V Figure 26-2. Maximum Frequency vs. VCC (10 -20 MHz). 20 MHz 10 MHz Safe Operating Area 2.7V 4.5V 5.
26.4 26.4.1 Clock Characterizations Calibrated Internal RC Oscillator Accuracy Table 26-1. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25⋅C ±10% User Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40⋅C - 85⋅C ±1% Notes: 26.4.2 1. Voltage range for ATmega325PV/3250PV/645PV/6450PV. 2. Voltage range for ATmega325P/3250P. External Clock Drive Waveforms Figure 26-3.
ATmega325P/3250P 26.5 System and Reset Characterizations Table 26-3. Reset, Brown-out, and Internal Voltage Reference Characteristics Symbol Parameter Condition VRST RESET Pin Threshold Voltage VCC = 3V tRST Minimum pulse width on RESET Pin VCC = 3V VHYST Min Typ 0.2 VCC Max Units 0.85 VCC V 800 ns Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 2.
Table 26-5. Reset, Brown-out and Internal Voltage Reference Characteristics(1), TA = -40°C to 85°C Symbol VPOT SRON Notes: 26.8 Parameter Min Typ Max Units Power-on Reset Threshold Voltage (rising) 1.1 1.4 1.6 V Power-on Reset Threshold Voltage (falling)(2) 0.6 1.3 1.6 V Power-on Slope Rate 0.01 10 V/ms 1. Values are guidelines only. Actual values are TBD. 2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling) Brown-out Detection Table 26-6.
ATmega325P/3250P 26.9 SPI Timing Characteristics See Figure 26-4 and Figure 26-5 for details. Table 26-7. SPI Timing Parameters Description Mode 1 SCK period Master See Table 17-4 on page 161 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 26-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 311 MSB 17 ...
ATmega325P/3250P 26.10 ADC Characteristics – Preliminary Data Table 26-8. Symbol ADC Characteristics Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200 kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz 2.
Table 26-8. Symbol ADC Characteristics Parameter Condition Min Typ Max Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Notes: 313 1. Voltage difference between channels.
ATmega325P/3250P 27. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
Figure 27-2. Active Supply Current vs. Frequenzy (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 25 5.5 V 5.0 V 20 ICC (mA) 4.5 V 15 4.0 V 10 3.3 V 5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 27-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. V CC INTERNAL RC OSCILLATOR, 8 MHz 12 85 °C 25 °C -40 °C 10 I CC(mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 2.5 85 °C 2 25 °C ICC (mA) -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 27.2 Idle Supply Current Figure 27-5. Idle Supply Current vs. Low Frequenzy (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0.6 0.5 5.5 V 5.0 V 0.4 ICC (mA) 4.5 V 4.0 V 0.3 3.3 V 0.2 2.7 V 1.8 V 0.1 0 0 0.1 0.2 0.3 0.4 0.
Figure 27-6. Idle Supply Current vs. Frequenzy (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 8 5.5V 7 5.0V 6 4.5V ICC (mA) 5 4.0V 4 3 3.3V 2 2.7V 1 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 27-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. V CC INTERNAL RC OSCILLATOR, 8 MHz 3.5 85 °C 25 °C -40 °C 3 ICC (mA) 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0.9 85 °C 0.8 25 °C 0.7 -40 °C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 27.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode.
It is possible to calculate the typical current consumption based on the numbers from Table 27-2 for other VCC and frequency settings than listed in Table 27-1. 27.3.1 Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 27-2 shows that we need to add 4.9% for the USART0, 5.9% for the SPI, and 2.6% for the TIMER1 module. From Figure 27-5, we find that the idle current consumption is ~0.21mA at VCC = 3.0V and F = 1MHz.
ATmega325P/3250P Figure 27-10. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 20 85 °C 18 -40 °C 16 25 °C 14 ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 27.5 Power-save Supply Current Figure 27-11. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 3.5 85 °C 3 ICC (uA) 2.5 2 1.5 25 °C 1 -40 °C 0.5 0 1.5 2 2.5 3 3.5 4 4.
27.6 Standby Supply Current Figure 27-12. Standby Supply Current vs. VCC (Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0.2 0.18 6MHz_xtal 6MHz_res 0.16 0.14 4MHz_res 4MHz_xtal ICC(mA) 0.12 0.1 2MHz_res 2MHz_xtal 1MHz_res 450kHz_res 0.08 0.06 0.04 0.02 32kHz_xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (MHz) 27.7 Pin Pull-up Figure 27-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8 V) I/O PIN PULL-UP RESISTOR CURRENT vs.
ATmega325P/3250P Figure 27-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7 V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE VCC = 2.7V 80 70 60 IOP (uA) 50 40 30 20 25 °C 10 85 °C -40 °C 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 27-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5 V) I/O PIN PULL-UP RESISTOR CURRENT vs.
Figure 27-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 1.8V 40 35 30 IRESET(uA) 25 20 15 10 25 °C -40 °C 5 85 °C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET(V) Figure 27-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 2.7V 70 60 IRESET(uA) 50 40 30 20 25 °C 10 -40 °C 85 °C 0 0 0.5 1 1.5 2 2.
ATmega325P/3250P Figure 27-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5 V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE VCC = 5V 120 100 IRESET(uA) 80 60 40 25 °C 20 -40 °C 85 °C 0 0 1 2 3 4 5 6 VRESET(V) 27.8 Pin Driver Strength Figure 27-19. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B VCC = 1.8V 14 12 -40 °C 10 25 °C IOL (mA) 85 °C 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
Figure 27-20. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B VCC = 2.7V 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 27-21. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B VCC = 5V 80 70 60 25 °C IOL (mA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega325P/3250P Figure 27-22. I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 1.8 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT A, C, D, E, F, G, H, J VCC 1.8V 7 6 -40 °C 5 25 °C IOL (mA) 85 °C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 27-23. I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 2.7 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT A, C, D, E, F, G, H, J I/O PIN SINK CURRENT vs.
Figure 27-24. I/O Pin Sink Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 5 V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT A,C, D, E, F, G, H, J VCC = 5V 40 35 30 25 °C IOL (mA) 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 VOL (V) Figure 27-25. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8 V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B VCC = 1.8V 8 -40 °C 7 25 °C 6 85 °C IOH (mA) 5 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.
ATmega325P/3250P Figure 27-26. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7 V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B VCC = 2.7V 25 25 °C IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 27-27. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 5 V) I/O PIN SOURCE CURRENT vs.
Figure 27-28. I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 1.8 V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT A, C, D, E, F, G, H, J VCC = 1.8V 6 -40 °C 5 25 °C 85 °C IOH (mA) 4 3 2 1 0 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 VOH (V) Figure 27-29. I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 2.7 V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT A, C, D, E, F, G, H, J VCC = 2.
ATmega325P/3250P Figure 27-30. I/O Pin Source Current vs. Output Voltage, Port A,C,D,E,F,G,H,J (VCC = 5 V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT A, C, D, E, F, G, H, J VCC = 5V 60 50 25 °C IOH (mA) 40 30 20 10 0 0 1 2 3 4 5 6 VOH (V) 27.9 Pin Threshold and Hysteresis Figure 27-31. I/O Pin Input Threshold Voltage vs. VCC, Port B (VIH, IO Pin Read as ¨1¨) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC, PORT B VIH, IO PIN READ AS '1' 3 -40 °C 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.
Figure 27-32. I/O Pin Input Threshold Voltage vs. VCC, Port B (VIL, IO Pin Read as ¨0¨) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC, PORT B VIL, IO PIN READ AS '0' 2.5 85 °C 25 °C Threshold (V) 2 -40 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-33. I/O Pin Input Hysteresis vs. VCC, Port B I/O PIN INPUT HYSTERESIS vs. VCC, PORT B 0.7 0.6 Input Hysteresis (mV) -40 °C 0.5 25 °C 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-34. I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIH, IO Pin Read as ¨1¨) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC, PORT A, C, D, E, F, G, H, J VIH, IO PIN READ AS '1' -40 °C 3 25 °C 85 °C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-35. I/O Pin Input Threshold Voltage vs. VCC, Port A,C,D,E,F,G,H,J (VIL, IO Pin Read as ¨0¨) I/O PIN INPUT THRESHOLD VOLTAGE vs.
Figure 27-36. I/O Pin Hysteresis vs. VCC, Port A,C,D,E,F,G,H,J I/O PIN INPUT HYSTERESIS vs. VCC, PORT A, C, D, E, F, G, H, J 0.7 Input Hysteresis (mV) 0.6 -40 °C 25 °C 0.5 85 °C 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-37. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ¨1¨) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 2.5 -40 °C 25 °C Threshold (V) 2 85 °C 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-38. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ¨0¨) RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-39. Reset Pin Input Hysteresis vs. VCC RESET PIN INPUT HYSTERESIS vs. VCC 0.7 Input Hysteresis (mV) 0.6 0.5 0.4 0.3 0.2 -40 °C 0.1 25 °C 85 °C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
27.10 Internal Oscillator Speed Figure 27-40. Watchdog Oscillator Frequenzy vs. VCC WATCHDOG OSCILLATOR FREQUENCY vs. VCC 170 -40 °C 25 °C FRC (kHz) 160 85 °C 150 140 130 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-41. Watchdog Oscillator Frequenzy vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 170 165 FRC (kHz) 160 5.5 V 155 4.0 V 3.3 V 2.7 V 150 145 2.
ATmega325P/3250P Figure 27-42. Calibrated 8 MHz RC Oscillator Frequenzy vs. VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC 8.4 85 °C 8.2 25 °C FRC (MHz) 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5,5 VCC (V) Figure 27-43. Calibrated 8 MHz RC Oscillator Frequenzy vs. Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE FRC (MHz) 8.4 8.2 5.5 V 4.0 3.3 V V 2.7 V 8 1.8 V 7.8 7.6 7.
Figure 27-44. Calibrated 8 MHz RC Oscillator Frequenzy vs. Osccal Value CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 85 °C 14 25 °C 12 -40 °C FRC (MHz) 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 27.11 Current Consumption of Peripheral Units Figure 27-45. Brownout Detector Current vs. VCC BROWNOUT DETECTOR CURRENT vs. VCC 30 85 °C 25 °C -40 °C 25 ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-46. ADC Current vs. VCC (AREF = AVCC) ADC CURRENT vs. VCC AREF = AVCC 500 450 400 -40 °C 350 25 °C ICC (uA) 300 85 °C 250 200 150 100 50 0 1.5 2 2.5 3 3.5 V 4 4.5 5 5.5 (V) Figure 27-47. AREF External Reference Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 180 -40 °C 160 25 °C 140 85 °C ICC (uA) 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
Figure 27-48. Watchdog Timer Current vs. VCC WATCHDOG TIMER CURRENT vs. VCC 18 -40 °C 16 85 °C 14 25 °C ICC (uA) 12 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 27-49. Analog Comparator Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 100 90 -40 °C 80 25 °C 85 °C 70 ICC (uA) 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325P/3250P Figure 27-50. Programming Current vs. VCC PROGRAMMING CURRENT vs. Vcc 12 -40 °C 25 °C 10 85 °C ICC (mA) 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 27.12 Current Consumption in Reset and Reset Pulswidth Figure 27-51. Reset Supply Current vs. Low Frequenzy (0.1 - 1.0 MHz) RESET SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 0.25 5.5 V 0.2 5.0 V ICC (mA) 4.5 V 0.15 4.0 V 3.3 V 0.1 2.7 V 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 27-52. Reset Supply Current vs. Frequenzy (1 - 20 MHz) RESET SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 4 5.5 V 3.5 5.0 V 3 4.5 V ICC (mA) 2.5 4.0 V 2 1.5 3.3 V 1 2.7 V 0.5 1.8 V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Figure 27-53. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs.
ATmega325P/3250P 28. Register Summary Note: Address Name Registers with bold type only available in ATmega3250P.
Address Name (0xC4) UBRR0L (0xC3) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - USART0 Baud Rate Register Low - - - - - Page 186 (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 184 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 183 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 182 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - -
ATmega325P/3250P Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x85) TCNT1H Timer/Counter1 High (0x84) TCNT1L Timer/Counter1 Low (0x83) Reserved - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 131 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 130 128 - - 132 132 - - - (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 205 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - COM0A0 WGM01 CS02 CS01 CS00 102 - - - PSR2 PSR10 105/153 - - 0x26 (0x46) TCNT0 Timer/Counter0 0x25 (0x45) Reserved - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 0x23 (0x43) GTCCR TSM - - 0x22 (0x42) EEARH - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - Page 104 EERIE EEPROM Address Register High 23 23 23 EE
ATmega325P/3250P 29.
Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), R
ATmega325P/3250P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
30. Ordering Information 30.1 ATmega325P Speed (MHz)(3) Power Supply 10 1.8 - 5.5V ATmega325PV-10AU ATmega325PV-10MU 64A 64M1 Industrial (-40⋅C to 85⋅C) 20 2.7 - 5.5V ATmega325P-20AU ATmega325P-20MU 64A 64M1 Industrial (-40⋅C to 85⋅C) Notes: Ordering Code(2) Package Type(1) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega325P/3250P 30.2 ATmega3250P Speed (MHz)(3) Power Supply 10 1.8 - 5.5V ATmega3250PV-10AU 100A Industrial (-40⋅C to 85⋅C) 20 2.7 - 5.5V ATmega3250P-20AU 100A Industrial (-40⋅C to 85⋅C) Notes: Ordering Code(2) Package Type(1) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
31. Packaging Information 31.1 64A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
ATmega325P/3250P 31.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e Pin #1 Notch (0.20 R) BOTTOM VIEW Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. D 8.
31.3 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.
ATmega325P/3250P 32. Errata 32.1 ATmega325P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer. • Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
32.4 ATmega3250P rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer. • Using BOD disable will make the chip reset. 1. Interrupts may be lost when writing the timer registers in the asynchronous timer. The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega325P/3250P 33. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 33.1 Rev.8023F– 07/09 1. 2. 33.2 Rev.8023E– 06/08 1. 2. 3. 4. 5. 6. 7. 33.3 Updated ”Errata” on page 354. Rev.8023B – 08/07 1. 2. 3. 4. 33.6 Added ”Data Retention” on page 10. Updated Device and JTAG ID in ”Signature Bytes” on page 274. Rev.8023C – 08/07 1. 33.
ATmega325P/3250P Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1Disclaimer ..................................................................................................................3 2 Overview ................................................................................................... 3 2.
8.6Calibrated Internal RC Oscillator .............................................................................33 8.7External Clock .........................................................................................................34 8.8Clock Output Buffer .................................................................................................35 8.9Timer/Counter Oscillator .........................................................................................35 8.
ATmega325P/3250P 13.2Ports as General Digital I/O ...................................................................................64 13.3Alternate Port Functions ........................................................................................69 13.4Register Description ..............................................................................................85 14 8-bit Timer/Counter0 with PWM ............................................................ 89 14.1Features .......................
16.9Asynchronous Operation of Timer/Counter2 .......................................................147 16.10Register Description ..........................................................................................149 17 SPI – Serial Peripheral Interface ......................................................... 154 17.1Features ..............................................................................................................154 17.2Overview ................................................
ATmega325P/3250P 21.4Starting a Conversion ..........................................................................................208 21.5Prescaling and Conversion Timing ......................................................................209 21.6Changing Channel or Reference Selection .........................................................211 21.7ADC Noise Canceler ...........................................................................................212 21.8ADC Conversion Result ...............
24.9Register Description ............................................................................................269 25 Memory Programming ......................................................................... 271 25.1Program And Data Memory Lock Bits .................................................................271 25.2Fuse Bits .............................................................................................................272 25.3Signature Bytes ....................................
ATmega325P/3250P 29 Instruction Set Summary .................................................................... 346 30 Ordering Information ........................................................................... 349 30.1ATmega325P ......................................................................................................349 30.2ATmega3250P ....................................................................................................350 31 Packaging Information ........................
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