Datasheet

98
2570N–AVR–05/11
ATmega325/3250/645/6450
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 93 for more details.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.9.2 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.
15.9.3 OCR0A – Output Compare Register A
Table 15-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
01Reserved
1 0 Clear OC0A on compare match when up-counting. Set OC0A on
compare match when counting down.
1 1 Set OC0A on compare match when up-counting. Clear OC0A on
compare match when counting down.
Table 15-6. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
001clk
I/O
/(No prescaling)
010clk
I/O
/8 (From prescaler)
011clk
I/O
/64 (From prescaler)
100clk
I/O
/256 (From prescaler)
101clk
I/O
/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 76543210
0x26 (0x46) TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Bit 76543210
0x27 (0x47) OCR0A[7:0] OCR0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000