Datasheet

40
2570N–AVR–05/11
ATmega325/3250/645/6450
10.9.2 PRR – Power Reduction Register
• Bits 7:4 - Reserved bits
These bits are reserved bits in Atmel ATmega325/3250/645/6450 and will always read as zero.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is
enabled, operation will continue like before the shutdown.
• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper
operation.
• Bit 1 - PRUSART: Power Reduction USART
Writing logic one to this bit shuts down the USART by stopping the clock to the module. When
waking up the USART again, the USART should be re-initialized to ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
The Analog Comparator is disabled using the ACD-bit in the “ACSR – Analog Comparator Control and Sta-
tus Register” on page 198.
Bit 7654 3 2 1 0
(0x64)
– – – – PRTIM1 PRSPI PRUSART0 PRADC PRR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0