Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 8-Bit 16 MHz I/O number 69

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Table Of Contents

Features
1. Pin Configurations
2. Overview
- 2.1 Block Diagram
- 2.2 Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450
- 2.3 Pin Descriptions
3. Resources
4. Data Retention
5. About Code Examples
6. Capacitive touch sensing
7. AVR CPU Core
- 7.1 Overview
- 7.2 Architectural Overview
- 7.3 ALU – Arithmetic Logic Unit
- 7.4 Status Register
  - 7.4.1 SREG – AVR Status Register
- 7.5 General Purpose Register File
  - 7.5.1 The X-register, Y-register, and Z-register
- 7.6 Stack Pointer
- 7.7 Instruction Execution Timing
- 7.8 Reset and Interrupt Handling
  - 7.8.1 Interrupt Response Time
8. AVR Memories
- 8.1 In-System Reprogrammable Flash Program Memory
- 8.2 SRAM Data Memory
  - 8.2.1 Data Memory Access Times
- 8.3 EEPROM Data Memory
- 8.4 I/O Memory
  - 8.4.1 General Purpose I/O Registers
- 8.5 Register Description
9. System Clock and Clock Options
- 9.1 Clock Systems and their Distribution
- 9.2 Clock Sources
  - 9.2.1 Default Clock Source
- 9.3 Crystal Oscillator
- 9.4 Low-frequency Crystal Oscillator
- 9.5 Calibrated Internal RC Oscillator
- 9.6 External Clock
- 9.7 Clock Output Buffer
- 9.8 Timer/Counter Oscillator
- 9.9 System Clock Prescaler
  - 9.9.1 Switching Time
- 9.10 Register Description
  - 9.10.1 OSCCAL – Oscillator Calibration Register
  - 9.10.2 CLKPR – Clock Prescale Register
10. Power Management and Sleep Modes
- 10.1 Sleep Modes
- 10.2 Idle Mode
- 10.3 ADC Noise Reduction Mode
- 10.4 Power-down Mode
- 10.5 Power-save Mode
- 10.6 Standby Mode
- 10.7 Power Reduction Register
- 10.8 Minimizing Power Consumption
- 10.9 Register Description
  - 10.9.1 SMCR – Sleep Mode Control Register
  - 10.9.2 PRR – Power Reduction Register
11. System Control and Reset
- 11.1 Resetting the AVR
- 11.2 Reset Sources
- 11.3 Power-on Reset
- 11.4 External Reset
- 11.5 Brown-out Detection
- 11.6 Watchdog Reset
- 11.7 Internal Voltage Reference
  - 11.7.1 Voltage Reference Enable Signals and Start-up Time
- 11.8 Watchdog Timer
- 11.9 Timed Sequences for Changing the Configuration of the Watchdog Timer
  - 11.9.1 Safety Level 1
  - 11.9.2 Safety Level 2
- 11.10 Register Description
  - 11.10.1 MCUSR – MCU Status Register
  - 11.10.2 WDTCR – Watchdog Timer Control Register
12. Interrupts
- 12.1 Interrupt Vectors in Atmel ATmega325/3250/645/6450
- 12.2 Moving Interrupts Between Application and Boot Space
- 12.3 Register Description
  - 12.3.1 MCUCR – MCU Control Register
13. External Interrupts
- 13.1 Pin Change Interrupt Timing
- 13.2 Register Description
14. I/O-Ports
- 14.1 Overview
- 14.2 Ports as General Digital I/O
- 14.3 Alternate Port Functions
- 14.4 Register Description
15. 8-bit Timer/Counter0 with PWM
- 15.1 Features
- 15.2 Overview
  - 15.2.1 Definitions
  - 15.2.2 Registers
- 15.3 Timer/Counter Clock Sources
- 15.4 Counter Unit
- 15.5 Output Compare Unit
- 15.6 Compare Match Output Unit
  - 15.6.1 Compare Output Mode and Waveform Generation
- 15.7 Modes of Operation
- 15.8 Timer/Counter Timing Diagrams
- 15.9 Register Description
16. Timer/Counter0 and Timer/Counter1 Prescalers
- 16.0.1 Internal Clock Source
- 16.0.2 Prescaler Reset
- 16.0.3 External Clock Source
- 16.1 Register Description
  - 16.1.1 GTCCR – General Timer/Counter Control Register
17. 16-bit Timer/Counter1
- 17.1 Features
- 17.2 Overview
- 17.3 Accessing 16-bit Registers
  - 17.3.1 Reusing the Temporary High Byte Register
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Output Compare Units
- 17.8 Compare Match Output Unit
  - 17.8.1 Compare Output Mode and Waveform Generation
- 17.9 Modes of Operation
- 17.10 Timer/Counter Timing Diagrams
- 17.11 Register Description
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 18.1 Features
- 18.2 Overview
  - 18.2.1 Registers
  - 18.2.2 Definitions
- 18.3 Timer/Counter Clock Sources
- 18.4 Counter Unit
- 18.5 Output Compare Unit
- 18.6 Compare Match Output Unit
  - 18.6.1 Compare Output Mode and Waveform Generation
- 18.7 Modes of Operation
- 18.8 Timer/Counter Timing Diagrams
- 18.9 Asynchronous Operation of Timer/Counter2
- 18.10 Timer/Counter Prescaler
- 18.11 Register Description
19. SPI – Serial Peripheral Interface
- 19.1 Features
- 19.2 Overview
- 19.3 SS Pin Functionality
  - 19.3.1 Slave Mode
  - 19.3.2 Master Mode
- 19.4 Data Modes
- 19.5 Register Description
20. USART0
- 20.1 Features
- 20.2 Overview
  - 20.2.1 AVR USART vs. AVR UART – Compatibility
- 20.3 Clock Generation
- 20.4 Frame Formats
  - 20.4.1 Parity Bit Calculation
- 20.5 USART Initialization
- 20.6 Data Transmission – The USART Transmitter
- 20.7 Data Reception – The USART Receiver
- 20.8 Asynchronous Data Reception
- 20.9 Multi-processor Communication Mode
  - 20.9.1 Using MPCMn
- 20.10 Examples of Baud Rate Setting
- 20.11 Register Description
21. USI – Universal Serial Interface
- 21.1 Overview
- 21.2 Functional Descriptions
- 21.3 Alternative USI Usage
- 21.4 Register Descriptions
22. Analog Comparator
- 22.1 Analog Comparator Multiplexed Input
- 22.2 Register Description
23. Analog to Digital Converter
- 23.1 Features
- 23.2 Operation
- 23.3 Starting a Conversion
- 23.4 Prescaling and Conversion Timing
- 23.5 Changing Channel or Reference Selection
  - 23.5.1 ADC Input Channels
  - 23.5.2 ADC Voltage Reference
- 23.6 ADC Noise Canceler
- 23.7 ADC Conversion Result
- 23.8 Register Description
24. JTAG Interface and On-chip Debug System
- 24.1 Features
- 24.2 Overview
- 24.3 TAP – Test Access Port
- 24.4 TAP Controller
- 24.5 Using the Boundary-scan Chain
- 24.6 Using the On-chip Debug System
- 24.7 On-chip Debug Specific JTAG Instructions
- 24.8 Using the JTAG Programming Capabilities
- 24.9 Bibliography
- 24.10 Register Description
  - 24.10.1 OCDR – On-chip Debug Register
25. IEEE 1149.1 (JTAG) Boundary-scan
- 25.1 Features
- 25.2 System Overview
- 25.3 Data Registers
- 25.4 Boundary-scan Specific JTAG Instructions
- 25.5 Boundary-scan Related Register in I/O Memory
  - 25.5.1 MCUCR – MCU Control Register
  - 25.5.2 MCUSR – MCU Status Register
- 25.6 Boundary-scan Chain
- 25.7 Boundary-scan Order
- 25.8 Boundary-scan Description Language Files
26. Boot Loader Support – Read-While-Write Self-Programming
- 26.1 Features
- 26.2 Overview
- 26.3 Application and Boot Loader Flash Sections
  - 26.3.1 Application Section
  - 26.3.2 BLS – Boot Loader Section
- 26.4 Read-While-Write and No Read-While-Write Flash Sections
  - 26.4.1 RWW – Read-While-Write Section
  - 26.4.2 NRWW – No Read-While-Write Section
- 26.5 Boot Loader Lock Bits
- 26.6 Entering the Boot Loader Program
- 26.7 Addressing the Flash During Self-Programming
- 26.8 Self-Programming the Flash
- 26.9 Register Description
  - 26.9.1 Store Program Memory Control and Status Register – SPMCSR
27. Memory Programming
- 27.1 Program And Data Memory Lock Bits
- 27.2 Fuse Bits
  - 27.2.1 Latching of Fuses
- 27.3 Signature Bytes
- 27.4 Calibration Byte
- 27.5 Parallel Programming Parameters, Pin Mapping, and Commands
  - 27.5.1 Signal Names
- 27.6 Parallel Programming
- 27.7 Serial Downloading
- 27.8 Programming via the JTAG Interface
28. Electrical Characteristics
- 28.1 Absolute Maximum Ratings*
- 28.2 DC Characteristics
- 28.3 Speed Grades
- 28.4 Clock Characteristics
- 28.5 System and Reset Characteristics
- 28.6 SPI Timing Characteristics
- 28.7 ADC
29. Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Supply Current of I/O modules
- 29.4 Power-down Supply Current
- 29.5 Power-save Supply Current
- 29.6 Standby Supply Current
- 29.7 Pin Pull-up
- 29.8 Pin Driver Strength
- 29.9 Pin Thresholds and hysteresis
- 29.10 BOD Thresholds and Analog Comparator Offset
- 29.11 Internal Oscillator Speed
- 29.12 Current Consumption of Peripheral Units
- 29.13 Current Consumption in Reset and Reset Pulsewidth
30. Register Summary
31. Instruction Set Summary
32. Ordering Information
- 32.1 ATmega325
- 32.2 ATmega3250
- 32.3 ATmega645
- 32.4 ATmega6450
33. Packaging Information
- 33.1 64A
- 33.2 64M1
- 33.3 100A
34. Errata
- 34.1 Errata ATmega325
- 34.2 Errata ATmega3250
- 34.3 Errata ATmega645
  - 34.3.1 ATmega645 Rev. A
- 34.4 Errata ATmega6450
  - 34.4.1 ATmega6450 Rev. A
35. Datasheet Revision History
- 35.1 Rev. 2570N – 05/11
- 35.2 Rev. 2570M – 04/11
- 35.3 Rev. 2570L – 08/07
- 35.4 Rev. 2570K – 04/07
- 35.5 Rev. 2570J – 11/06
- 35.6 Rev. 2570I – 07/06
- 35.7 Rev. 2570H – 06/06
- 35.8 Rev. 2570G – 04/06
- 35.9 Rev. 2570F – 03/06
- 35.10 Rev. 2570E – 03/06
- 35.11 Rev. 2570D – 05/05
- 35.12 Rev. 2570C – 11/04
- 35.13 Rev. 2570B – 09/04
- 35.14 Rev. 2570A – 09/04
Table of Contents

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2570N–AVR–05/11

ATmega325/3250/645/6450

• Bit 3 – USBSn: Stop Bit Select

This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores

this setting.

• Bit 2:1 – UCSZn1:0: Character Size

The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits

(Character SiZe) in a frame the Receiver and Transmitter use.

• Bit 0 – UCPOLn: Clock Polarity

This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is

used. The UCPOLn bit sets the relationship between data output change and data input sample,

and the synchronous clock (XCK).

Table 20-10. USBS Bit Settings

USBSn Stop Bit(s)

01-bit

12-bit

Table 20-11. UCSZ Bits Settings

UCSZn2 UCSZn1 UCSZn0 Character Size

0 0 0 5-bit

0 0 1 6-bit

0 1 0 7-bit

0118-bit

100Reserved

101Reserved

110Reserved

1 1 1 9-bit

Table 20-12. UCPOL Bit Settings

UCPOLn

Transmitted Data Changed

(Output of TxD Pin)

Received Data Sampled

(Input on RxD Pin)

0 Rising XCK Edge Falling XCK Edge

1 Falling XCK Edge Rising XCK Edge