Features • High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega325/ATmega3250) • 64KBytes (ATmega645/ATmega6450) – EEPROM • 1Kbytes (ATmeg
ATmega325/3250/645/6450 1. Pin Configurations DNC GND VCC DNC PA0 PA1 PA2 81 80 79 78 77 76 DNC 82 DNC PH4 (PCINT20) PF7 (ADC7/TDI) 89 83 PF6 (ADC6/TDO) 90 84 PF5 (ADC5/TMS) 91 PH6 (PCINT22) PF4 (ADC4/TCK) 92 PH5 (PCINT21) PF3 (ADC3) 93 85 PF2 (ADC2) 94 86 PF1(ADC1) 95 DNC PF0 (ADC0) 96 PH7 (PCINT23) AREF 97 87 AGND 98 88 AVCC 99 Pinout ATmega3250/6450 100 Figure 1-1.
ATmega325/3250/645/6450 DNC 1 (RXD/PCINT0) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 PA1 PA2 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega325/645 64 Figure 1-2.
ATmega325/3250/645/6450 2. Overview The Atmel ATmega325/3250/645/6450 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the Atmel ATmega325/3250/645/6450 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram GND Block Diagram PF0 - PF7 VCC PORTA DRIVERS PORTF DRIVERS DATA DIR. REG.
ATmega325/3250/645/6450 resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
ATmega325/3250/645/6450 2.2 Comparison between ATmega325, ATmega3250, ATmega645 and ATmega6450 The ATmega325, ATmega3250, ATmega645, and ATmega6450 differ only in memory sizes, pin count and pinout. Table 2-1 on page 6 summarizes the different configurations for the four devices. Table 2-1. 2.
ATmega325/3250/645/6450 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega325/3250/645/6450 2.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.
ATmega325/3250/645/6450 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
ATmega325/3250/645/6450 7. AVR CPU Core 7.1 Overview This section discusses the Atmel® AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1.
ATmega325/3250/645/6450 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.
ATmega325/3250/645/6450 7.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
ATmega325/3250/645/6450 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
ATmega325/3250/645/6450 Figure 7-3. The X-, Y-, and Z-registers 15 XH XL 7 X-register 0 R27 (0x1B) YH YL 7 0 R29 (0x1D) Z-register 0 R26 (0x1A) 15 Y-register 0 7 0 7 0 R28 (0x1C) 15 ZH 7 0 ZL 7 R31 (0x1F) 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.
ATmega325/3250/645/6450 ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4.
ATmega325/3250/645/6450 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag.
ATmega325/3250/645/6450 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
ATmega325/3250/645/6450 8. AVR Memories This section describes the different memories in the Atmel ATmega325/3250/645/6450. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the Atmel ATmega325/3250/645/6450 features an EEPROM Memory for data storage. All three memory spaces are linear. 8.
ATmega325/3250/645/6450 8.2 SRAM Data Memory Figure 8-2 on page 19 shows how the Atmel ATmega325/3250/645/6450 SRAM Memory is organized. The Atmel ATmega325/3250/645/6450 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
ATmega325/3250/645/6450 Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address valid Write Data WR Read Data RD Memory Access Instruction 8.3 Next Instruction EEPROM Data Memory The Atmel ATmega325/3250/645/6450 contains 1/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
ATmega325/3250/645/6450 consequence, the device does not enter Power-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down. 8.3.3 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.
ATmega325/3250/645/6450 8.5 8.5.
ATmega325/3250/645/6450 • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
ATmega325/3250/645/6450 Table 8-1. EEPROM Programming Time Number of Calibrated RC Oscillator Cycles Symbol EEPROM write (from CPU) Typical Programming Time 27,072 3.4ms The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software.
ATmega325/3250/645/6450 Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from Data Register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<
ATmega325/3250/645/6450 9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 on page 26 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 35. The clock systems are detailed below. Figure 9-1.
ATmega325/3250/645/6450 9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
ATmega325/3250/645/6450 9.3 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 9-2 on page 28. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment.
ATmega325/3250/645/6450 Table 9-4. Start-up Times for the Crystal Oscillator Clock Selection (Continued) CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save 0 11 1K CK(2) 14CK + 4.1ms Ceramic resonator, fast rising power 1 00 1K CK(2) 14CK + 65ms Ceramic resonator, slowly rising power 01 16K CK 14CK 10 16K CK 14CK + 4.1ms Crystal Oscillator, fast rising power 11 16K CK 14CK + 65ms Crystal Oscillator, slowly rising power 1 1 1 Note: Additional Delay from Reset (VCC = 5.
ATmega325/3250/645/6450 This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9-7 on page 30. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 28-2 on page 300.
ATmega325/3250/645/6450 Figure 9-3. External Clock Drive Configuration NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-10 on page 31. Table 9-10. Start-up Times for the External Clock Selection SUT1..0 Start-up Time from Powerdown and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK 14CK 01 6 CK 14CK + 4.
ATmega325/3250/645/6450 Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See “Asynchronous Operation of Timer/Counter2” on page 141 for further description on selecting external clock as input instead of a 32kHz crystal. 9.9 System Clock Prescaler The Atmel ATmega325/3250/645/6450 system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 33.
ATmega325/3250/645/6450 The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. 9.10.
ATmega325/3250/645/6450 Table 9-11.
ATmega325/3250/645/6450 10. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 10.1 Sleep Modes Figure 9-1 on page 26 presents the different clock systems in the Atmel ATmega325/3250/645/6450, and their distribution. The figure is helpful in selecting an appropriate sleep mode.
ATmega325/3250/645/6450 Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 10.3 ADC Noise Reduction Mode When the SM2..
ATmega325/3250/645/6450 10.6 Standby Mode When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles. 10.
ATmega325/3250/645/6450 above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 44 for details on the start-up time. 10.8.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off.
ATmega325/3250/645/6450 10.9 10.9.1 Register Description SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. Table 10-2.
ATmega325/3250/645/6450 10.9.2 PRR – Power Reduction Register Bit 7 6 5 4 3 2 1 0 (0x64) – – – – PRTIM1 PRSPI PRUSART0 PRADC Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 PRR • Bits 7:4 - Reserved bits These bits are reserved bits in Atmel ATmega325/3250/645/6450 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing logic one to this bit shuts down the Timer/Counter1 module.
ATmega325/3250/645/6450 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
ATmega325/3250/645/6450 Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [1..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 301.
ATmega325/3250/645/6450 Figure 11-3. MCU Start-up, RESET Extended Externally VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 11.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 301) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
ATmega325/3250/645/6450 Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to page 45 for details on operation of the Watchdog Timer. Figure 11-6. Watchdog Reset During Operation CC CK 11.
ATmega325/3250/645/6450 Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 11.8 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz.
ATmega325/3250/645/6450 Table 11-2. Watchdog Timer Prescale Select WDP2 WDP1 WDP0 Number of WDT Oscillator Cycles Typical Time-out at VCC = 3.0V Typical Time-out at VCC = 5.0V 0 0 0 16K cycles 17.1ms 16.3ms 0 0 1 32K cycles 34.3ms 32.5ms 0 1 0 64K cycles 68.5ms 65ms 0 1 1 128K cycles 0.14s 0.13s 1 0 0 256K cycles 0.27s 0.26s 1 0 1 512K cycles 0.55s 0.52s 1 1 0 1,024K cycles 1.1s 1.0s 1 1 1 2,048K cycles 2.2s 2.
ATmega325/3250/645/6450 11.9.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE.
ATmega325/3250/645/6450 To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 11.10.
ATmega325/3250/645/6450 12. Interrupts This section describes the specifics of the interrupt handling as performed in Atmel ATmega325/3250/645/6450. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 12.1 Interrupt Vectors in Atmel ATmega325/3250/645/6450 Table 12-1. Note: Reset and Interrupt Vectors Vector No.
ATmega325/3250/645/6450 Table 12-2 on page 50 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 12-2.
ATmega325/3250/645/6450 0x002 2 jmp USI_OVF ; USI Overflow Handler 0x002 4 jmp ANA_COMP ; Analog Comparator Handler 0x002 6 jmp ADC ; ADC Conversion Complete Handler 0x002 8 jmp EE_RDY ; EEPROM Ready Handler 0x002 A jmp SPM_RDY ; SPM Ready Handler ;NOT_USED ; RESERVED 0x002 C 0x002 E jmp PCINT2 ; PCINT2 Handler 0x003 0 jmp PCINT3 ; PCINT3 Handler ldi r16, high(RAMEND) ; Main program start 0x003 3 out SPH,r16 ; Set Stack Pointer to top of RAM 0x003 4 ldi r16, low(RAMEND
ATmega325/3250/645/6450 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments 0x0000 RESET: ldi r16,high(RAMEND); Main program start 0x0001 out SPH,r16 0x0002 ldi r16,low(RAMEND) 0x0003 0x0004 out sei SPL,r16 0x0005 xxx ; Set Stack Pointer to top of RAM ; Enabl
ATmega325/3250/645/6450 When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x3800/0x7800 0x3800/0x7800 jmp 0x3802/0x7802 jmp RESET EXT_INT0 ; Reset handler ; IRQ0 Handler 0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler ... ... ...
ATmega325/3250/645/6450 in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-WhileWrite Self-Programming” on page 251 for details on Boot Lock bits. • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written.
ATmega325/3250/645/6450 13. External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT30..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT30..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. The pin change interrupt PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles.
ATmega325/3250/645/6450 Figure 13-1. Pin Change Interrupt pin_lat PCINT(0) D pcint_in_(0) Q 0 pcint_syn pcint_setflag PCIF pin_sync LE x clk PCINT(0) in PCMSK(x) clk clk PCINT(n) pin_lat pin_sync pcint_in_(n) pcint_syn pcint_setflag PCIF 13.2 13.2.1 Register Description EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control.
ATmega325/3250/645/6450 13.2.2 EIMSK – External Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 PCIE3 PCIE2 PCIE1 PCIE0 – – – INT0 Read/Write R/W R/W R/W R/W R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x1D (0x3D) EIMSK • Bit 7 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT30..24 pin will cause an interrupt.
ATmega325/3250/645/6450 corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This bit is reserved bit in ATmega325/645 and will always be read as zero. • Bit 6– PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT24..16 pin triggers an interrupt request, PCIF2 becomes set (one).
ATmega325/3250/645/6450 • Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16 Each PCINT23:16 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Note: 13.2.6 1. PCMSK3 and PCMSK2 are only present in ATmega3250/6450.
ATmega325/3250/645/6450 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
ATmega325/3250/645/6450 Functions” on page 66. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2.
ATmega325/3250/645/6450 be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
ATmega325/3250/645/6450 Figure 14-3.
ATmega325/3250/645/6450 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge.
ATmega325/3250/645/6450 Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
ATmega325/3250/645/6450 ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down.
ATmega325/3250/645/6450 Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
ATmega325/3250/645/6450 14.3.1 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-3. Table 14-3. Port Pin Port B Pins Alternate Functions Alternate Functions PB7 OC2A/PCINT15 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt15). PB6 OC1B/PCINT14 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt14). PB5 OC1A/PCINT13 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt13).
ATmega325/3250/645/6450 • OC1A/PCINT13, Bit 5 OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT13, Pin Change Interrupt Source 13: The PB5 pin can serve as an external interrupt source.
ATmega325/3250/645/6450 Table 14-4 and Table 14-5 relate the alternate functions of Port B to the overriding signals shown in Figure 14-5 on page 66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 14-4.
ATmega325/3250/645/6450 14.3.2 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-6. Table 14-6. Port Pin Port D Pins Alternate Functions Alternate Function PD7 - PD6 - PD5 - PD4 - PD3 - PD2 - PD1 INT0 (External Interrupt0 Input) PD0 ICP1 (Timer/Counter1 Input Capture pin) The alternate pin configuration is as follows: • INT0 – Port D, Bit 1 INT0, External Interrupt Source 0. The PD1 pin can serve as an external interrupt source to the MCU.
ATmega325/3250/645/6450 14.3.3 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 14-8. Table 14-8.
ATmega325/3250/645/6450 • XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in synchronous mode. AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. PCINT2, Pin Change Interrupt Source 2: The PE2 pin can serve as an external interrupt source.
ATmega325/3250/645/6450 Table 14-10.
ATmega325/3250/645/6450 • TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out data, the TDO pin drives actively. In other states the pin is pulled high. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5.
ATmega325/3250/645/6450 Table 14-13. Overriding Signals for Alternate Functions in PF3:PF0 14.3.5 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE – – – – DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT Alternate Functions of Port G The alternate pin configuration is as follows: Table 14-14.
ATmega325/3250/645/6450 Table 14-15. Overriding Signals for Alternate Functions in PG4 and PG3 14.3.6 Signal Name PG4/T0 PG3/T1 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – – DIEOE 0 0 DIEOV 0 0 DI T0 INPUT T1 INPUT AIO - - Alternate Functions of Port H Port H is only present in ATmega3250/6450. The alternate pin configuration is as follows: Table 14-16.
ATmega325/3250/645/6450 • PCINT20 – Port H, Bit 4 PCINT20, Pin Change Interrupt Source 20: The PH4 pin can serve as an external interrupt source. • PCINT19 – Port H, Bit 3 PCINT19, Pin Change Interrupt Source 19: The PH3 pin can serve as an external interrupt source. • PCINT18 – Port H, Bit 2 PCINT18, Pin Change Interrupt Source 18: The PH2 pin can serve as an external interrupt source. • PCINT17 – Port H, Bit 1 PCINT17, Pin Change Interrupt Source 17: The P1 pin can serve as an external interrupt source.
ATmega325/3250/645/6450 Table 14-18. Overriding Signals for Alternate Functions in PH3:0 14.3.
ATmega325/3250/645/6450 • PCINT27 – Port J, Bit 3 PCINT27, Pin Change Interrupt Source 27: The PE27 pin can serve as an external interrupt source. • PCINT26 – Port J, Bit 2 PCINT26, Pin Change Interrupt Source 26: The PE26 pin can serve as an external interrupt source. • PCINT25 – Port J, Bit 1 PCINT25, Pin Change Interrupt Source 25: The PE25 pin can serve as an external interrupt source.
ATmega325/3250/645/6450 Table 14-21. Overriding Signals for Alternate Functions in PH3:0 14.4 14.4.
ATmega325/3250/645/6450 14.4.5 PORTB – Port B Data Register Bit 14.4.6 7 6 5 4 3 2 1 0 0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRB – Port B Data Direction Register Bit 14.4.
ATmega325/3250/645/6450 14.4.13 PIND – Port D Input Pins Address Bit 14.4.14 7 6 5 4 3 2 1 0 0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A PORTE – Port E Data Register Bit 14.4.
ATmega325/3250/645/6450 14.4.21 14.4.22 14.4.
ATmega325/3250/645/6450 15. 8-bit Timer/Counter0 with PWM 15.1 Features Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • • • • • • • 15.
ATmega325/3250/645/6450 The definitions in Table 15-1 are also used extensively throughout the document. Table 15-1. BOTTOM MAX TOP 15.2.2 Definitions of Timer/Counter values. The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register.
ATmega325/3250/645/6450 15.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 15-2 shows a block diagram of the counter and its surroundings. Figure 15-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count clear TCNTn Control Logic clkTn Edge Detector Tn direction ( From Prescaler ) bottom top Signal description (internal signals): count Increment or decrement TCNT0 by 1.
ATmega325/3250/645/6450 Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 90.). Figure 15-3 shows a block diagram of the Output Compare unit. Figure 15-3.
ATmega325/3250/645/6450 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
ATmega325/3250/645/6450 Figure 15-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCn Waveform Generator D Q 1 OCnx DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
ATmega325/3250/645/6450 15.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero.
ATmega325/3250/645/6450 the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00.
ATmega325/3250/645/6450 In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 15-4 on page 97). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output.
ATmega325/3250/645/6450 Figure 15-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCn (COMnx1:0 = 2) OCn (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
ATmega325/3250/645/6450 • 15.8 The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set.
ATmega325/3250/645/6450 Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM OCRnx BOTTOM + 1 TOP OCFnx 15.9 15.9.
ATmega325/3250/645/6450 Waveform Generation Mode Bit Description(1) Table 15-2. Mode WGM01 (CTC0) WGM00 (PWM0) Timer/Counter Mode of Operation TOP Update of OCR0A at TOV0 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0A Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
ATmega325/3250/645/6450 Compare Output Mode, Phase Correct PWM Mode(1) Table 15-5. COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 Reserved 1 0 Clear OC0A on compare match when up-counting. Set OC0A on compare match when counting down. 1 1 Set OC0A on compare match when up-counting. Clear OC0A on compare match when counting down. Note: Description 1. A special case occurs when OCR0A equals TOP and COM0A1 is set.
ATmega325/3250/645/6450 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 15.9.
ATmega325/3250/645/6450 16.0.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. 16.0.
ATmega325/3250/645/6450 and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 16-1. Prescaler for Timer/Counter0 and Timer/Counter1(1) clk I/O Clear PSR10 T0 Synchronization T1 Synchronization clkT1 Note: 16.1 16.1.1 clkT0 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 1.
ATmega325/3250/645/6450 17. 16-bit Timer/Counter1 17.1 Features The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • • • • • • • • • • • 17.2 True 16-bit Design (i.e.
ATmega325/3250/645/6450 Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 17.2.1 TCCRnB 1.
ATmega325/3250/645/6450 put Compare Units” on page 111. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 197.
ATmega325/3250/645/6450 access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle.
ATmega325/3250/645/6450 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega325/3250/645/6450 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
ATmega325/3250/645/6450 17.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surroundings. Figure 17-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.
ATmega325/3250/645/6450 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 17.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit.
ATmega325/3250/645/6450 tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 104. 17.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
ATmega325/3250/645/6450 cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 17.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle.
ATmega325/3250/645/6450 prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly.
ATmega325/3250/645/6450 Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 17-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin.
ATmega325/3250/645/6450 A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 17.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits.
ATmega325/3250/645/6450 Figure 17-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega325/3250/645/6450 The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
ATmega325/3250/645/6450 to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values.
ATmega325/3250/645/6450 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11).
ATmega325/3250/645/6450 implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running.
ATmega325/3250/645/6450 the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction.
ATmega325/3250/645/6450 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
ATmega325/3250/645/6450 Figure 17-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCRnx OCFnx Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
ATmega325/3250/645/6450 Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 17.11 Register Description 17.11.
ATmega325/3250/645/6450 Table 17-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Table 17-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
ATmega325/3250/645/6450 Waveform Generation Mode Bit Description(1) Table 17-5.
ATmega325/3250/645/6450 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description.
ATmega325/3250/645/6450 A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 17.11.
ATmega325/3250/645/6450 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
ATmega325/3250/645/6450 • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
ATmega325/3250/645/6450 18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • • • • • • • 18.
ATmega325/3250/645/6450 18.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
ATmega325/3250/645/6450 Figure 18-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value.
ATmega325/3250/645/6450 Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
ATmega325/3250/645/6450 The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. 18.
ATmega325/3250/645/6450 18.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the OC2A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 18-3 on page 144. For fast PWM mode, refer to Table 18-4 on page 144, and for phase correct PWM refer to Table 18-5 on page 144.
ATmega325/3250/645/6450 Figure 18-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
ATmega325/3250/645/6450 PWM mode is shown in Figure 18-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 18-6.
ATmega325/3250/645/6450 18.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A while counting up, and set on the compare match while counting down.
ATmega325/3250/645/6450 decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N ⋅ 510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
ATmega325/3250/645/6450 Figure 18-8. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 18-9 shows the setting of OCF2A in all modes except CTC mode. Figure 18-9. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 18-10 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
ATmega325/3250/645/6450 18.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3.
ATmega325/3250/645/6450 cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge.
ATmega325/3250/645/6450 For Timer/Counter2, the possible prescaled selections are: clk T2S /8, clk T2S /32, clk T2S /64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 18.11 Register Description 18.11.
ATmega325/3250/645/6450 • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting.
ATmega325/3250/645/6450 • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 18-6. Table 18-6. 18.11.2 Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
ATmega325/3250/645/6450 • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
ATmega325/3250/645/6450 18.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – – OCF2A TOV2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector.
ATmega325/3250/645/6450 19. SPI – Serial Peripheral Interface 19.1 Features The Atmel ATmega325/3250/645/6450 SPI includes the following features: • • • • • • • • 19.
ATmega325/3250/645/6450 The interconnection between Master and Slave CPUs with SPI is shown in Figure 19-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
ATmega325/3250/645/6450 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 19-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 66. Table 19-1. Pin SPI Pin Overrides(1) Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
ATmega325/3250/645/6450 The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.
ATmega325/3250/645/6450 The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
ATmega325/3250/645/6450 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 19.3.
ATmega325/3250/645/6450 Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) LSB first (DORD = 1) 19.
ATmega325/3250/645/6450 • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set.
ATmega325/3250/645/6450 19.5.2 SPSR – SPI Status Register Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 0x2D (0x4D) SPSR • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag.
ATmega325/3250/645/6450 20. USART0 20.1 Features The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • • • • • • • • • • • • 20.
ATmega325/3250/645/6450 Figure 20-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
ATmega325/3250/645/6450 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode.
ATmega325/3250/645/6450 Figure 20-2. Clock Generation Logic, Block Diagram UBRR U2X fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 0 1 0 OSC DDR_XCK xcki XCK Pin Sync Register Edge Detector 0 UCPOL txclk UMSEL 1 xcko DDR_XCK 1 1 0 rxclk Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki operation. 20.3.1 Input from XCK pin (internal Signal). Used for synchronous slave xcko Clock output to XCK pin (Internal Signal).
ATmega325/3250/645/6450 Table 20-1.
ATmega325/3250/645/6450 or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 20-3. Synchronous Mode XCK Timing. UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample The UCPOLn bit in UCSRnC selects which XCK clock edge is used for data sampling and which is used for data change.
ATmega325/3250/645/6450 Figure 20-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
ATmega325/3250/645/6450 Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn Flag can be used to check that the Transmitter has completed all transfers, and the RXCn Flag can be used to check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose.
ATmega325/3250/645/6450 More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. 20.
ATmega325/3250/645/6450 The function simply waits for the transmit buffer to be empty by checking the UDREn Flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. 20.6.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn.
ATmega325/3250/645/6450 The Data Register Empty (UDREn) Flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compatibility with future devices, always write this bit to zero when writing the UCSRnA Register.
ATmega325/3250/645/6450 The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used.
ATmega325/3250/645/6450 The following code example shows a simple USART receive function that handles both nine bit characters and the status bits.
ATmega325/3250/645/6450 20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
ATmega325/3250/645/6450 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 20.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e.
ATmega325/3250/645/6450 Figure 20-5. Start Bit Sampling RxD IDLE START BIT 0 Sample (U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2X = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure.
ATmega325/3250/645/6450 Figure 20-7. Stop Bit Sampling and Next Start Bit Sampling RxD STOP 1 (A) (B) (C) Sample (U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2X = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
ATmega325/3250/645/6450 Table 20-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D # (Data+Parity Bit) Rslow (%) Rfast (%) Max Total Error (%) Recommended Max Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 20-3.
ATmega325/3250/645/6450 nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
ATmega325/3250/645/6450 20.10 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 20-4. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
ATmega325/3250/645/6450 Table 20-5. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864 MHz fosc = 4.0000 MHz fosc = 7.3728 MHz Baud Rate (bps) UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.
ATmega325/3250/645/6450 Table 20-6. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592 MHz fosc = 8.0000 MHz fosc = 14.7456 MHz Baud Rate (bps) UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.
ATmega325/3250/645/6450 Table 20-7. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000 MHz fosc = 18.4320 MHz fosc = 20.0000 MHz Baud Rate (bps) UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.
ATmega325/3250/645/6450 The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-ModifyWrite instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO. 20.11.
ATmega325/3250/645/6450 • Bit 1 – U2Xn: Double the USART Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using synchronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. • Bit 0 – MPCMn: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode.
ATmega325/3250/645/6450 • Bit 2 – UCSZn2: Character Size The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 1 – RXB8n: Receive Data Bit 8 RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn.
ATmega325/3250/645/6450 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 20-10. USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 20-11.
ATmega325/3250/645/6450 20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers Bit 15 14 13 12 – – – – 11 10 9 8 UBRRn[11:8] UBRRnH UBRRn[7:0] 7 Read/Write Initial Value 6 5 UBRRnL 4 3 2 1 0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written.
ATmega325/3250/645/6450 21. USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. The main features of the USI are: • • • • • • 21.
ATmega325/3250/645/6450 an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus.
ATmega325/3250/645/6450 Figure 21-3. Three-wire Mode, Timing Diagram CYCLE ( Reference ) 1 2 3 4 5 6 7 8 USCK USCK DO MSB DI MSB A B C 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB D E The Three-wire mode timing is shown in Figure 21-3. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes.
ATmega325/3250/645/6450 rjmp SPITransfer_loop lds r16,USIDR ret The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is called is transferred to the Slave device, and when the transfer is completed the data received from the Slave is stored back into the r16 Register.
ATmega325/3250/645/6450 21.2.3 SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ldi r16,(1<
ATmega325/3250/645/6450 Figure 21-4. Two-wire Mode Operation, Simplified Diagram VCC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL HOLD SCL Two-wire Clock Control Unit SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 SDA Bit0 SCL PORTxn MASTER Figure 21-4 shows two USI units operating in Two-wire mode, one as Master and one as Slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used.
ATmega325/3250/645/6450 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift Register, or by setting the corresponding bit in the PORT Register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The slave device’s start detector logic (Figure 21-6.) detects the start condition and sets the USISIF Flag.
ATmega325/3250/645/6450 trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the actual data rate in two-wire mode. 21.3 Alternative USI Usage When the USI unit is not used for serial communication, it can be set up to do alternative tasks due to its flexible design. 21.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact and higher performance UART than by software only. 21.3.
ATmega325/3250/645/6450 Note that the corresponding Data Direction Register to the pin must be set to one for enabling data output from the Shift Register. 21.4.2 USISR – USI Status Register Bit 7 6 5 4 3 2 1 0 USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB9) USISR The Status Register contains Interrupt Flags, line Status Flags and the counter value.
ATmega325/3250/645/6450 21.4.3 USICR – USI Control Register Bit 7 6 5 4 3 2 1 0 USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Read/Write R/W R/W R/W R/W R/W R/W W W Initial Value 0 0 0 0 0 0 0 0 (0xB8) USICR The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. • Bit 7 – USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt.
ATmega325/3250/645/6450 Table 21-1. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal. 0 1 Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORT Register in this mode. However, the corresponding DDR bit still controls the data direction. When the port pin is set as input the pins pull-up is controlled by the PORT bit.
ATmega325/3250/645/6450 • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS1..
ATmega325/3250/645/6450 22. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
ATmega325/3250/645/6450 22.1 Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..
ATmega325/3250/645/6450 • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
ATmega325/3250/645/6450 • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 22-2. Table 22-2. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge.
ATmega325/3250/645/6450 23. Analog to Digital Converter 23.1 Features • • • • • • • • • • • • • 10-bit Resolution 0.5 LSB Integral Non-linearity ± 2 LSB Absolute Accuracy 13µs - 260µs Conversion Time (50kHz to 1MHz ADC clock) Up to 76.9kSPS at Maximum Resolution (200kHz ADC clock) Eight Multiplexed Single Ended Input Channels Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 1.
ATmega325/3250/645/6450 Figure 23-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 15 TRIGGER SELECT ADC[9:0] ADPS0 ADPS1 ADIF ADPS2 ADATE ADEN ADSC 0 ADC DATA REGISTER (ADCH/ADCL) ADC CTRL.
ATmega325/3250/645/6450 If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost.
ATmega325/3250/645/6450 If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 23.4 Prescaling and Conversion Timing Figure 23-3.
ATmega325/3250/645/6450 with Auto triggering from a source other than the ADC Conversion Complete, each conversion will require 25 ADC clocks. This is because the ADC must be disabled and re-enabled after every conversion. In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 23-1. Figure 23-4.
ATmega325/3250/645/6450 Figure 23-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 23-1. ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 Condition Auto Triggered conversions 23.
ATmega325/3250/645/6450 23.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection.
ATmega325/3250/645/6450 23.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 23-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path).
ATmega325/3250/645/6450 Figure 23-9. ADC Power Connections VCC GND 52 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 61 AREF 62 10μΗ GND AVCC 100nF Analog Ground Plane 23.6.3 51 63 64 1 DNC PA0 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
ATmega325/3250/645/6450 • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 23-11. Gain Error Gain Error Output Code Ideal ADC Actual ADC VREF Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code.
ATmega325/3250/645/6450 • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 23-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 23.7 VREF Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.
ATmega325/3250/645/6450 Figure 23-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts) 0x200 Table 23-2. Correlation Between Input Voltage and Output Codes VADCn Read Code VADCm + VREF 0x1FF 511 VADCm + 511/512 VREF 0x1FF 511 510 0x1FE 510 VADCm + /512 VREF Corresponding Decimal Value ... ... ... VADCm + 1/512 VREF 0x001 1 VADCm 0x000 0 VADCm - /512 VREF 0x3FF -1 ... ... ...
ATmega325/3250/645/6450 23.8 23.8.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7C) ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 23-3.
ATmega325/3250/645/6450 Table 23-4. Input Channel Selections MUX4..
ATmega325/3250/645/6450 23.8.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
ATmega325/3250/645/6450 • Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 23-5. 23.8.
ATmega325/3250/645/6450 • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 211. 23.8.4 ADCSRB – ADC Control and Status Register B Bit 7 6 5 4 3 2 1 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADCSRB • Bit 7 – Reserved Bit This bit is reserved for future use.
ATmega325/3250/645/6450 24. JTAG Interface and On-chip Debug System 24.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
ATmega325/3250/645/6450 • TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP pins are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
ATmega325/3250/645/6450 Figure 24-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.
ATmega325/3250/645/6450 • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The ExitIR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
ATmega325/3250/645/6450 A debugger, like the AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 222. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
ATmega325/3250/645/6450 24.8 Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG programming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the JTAG Test Access Port.
ATmega325/3250/645/6450 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
ATmega325/3250/645/6450 25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 25.3.2 Device Identification Register Figure 25-1 shows the structure of the Device Identification Register. Figure 25-1.
ATmega325/3250/645/6450 Sources” on page 27) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 25-2. Figure 25-2. Reset Register To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 25.3.
ATmega325/3250/645/6450 25.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32 bit ID-Register as Data Register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: 25.4.3 • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input.
ATmega325/3250/645/6450 software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system. If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface. 25.5.2 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
ATmega325/3250/645/6450 Figure 25-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function.
ATmega325/3250/645/6450 Figure 25-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR WDx RESET OCxn DATA BUS RDx Pxn 1 Q ODxn IDxn D 0 PORTxn Q CLR RESET SLEEP WPx RRx SYNCHRONIZER D Q L Q D WRx RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 25.6.
ATmega325/3250/645/6450 25.6.3 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscillator, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 25-6 shows how each Oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock output is attached to an observe-only cell.
ATmega325/3250/645/6450 25.6.4 Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 25-7. The Boundary-scan cell from Figure 25-8 is attached to each of these signals. The signals are described in Table 25-4. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 25-7.
ATmega325/3250/645/6450 Table 25-4.
ATmega325/3250/645/6450 Table 25-5.
ATmega325/3250/645/6450 Table 25-5.
ATmega325/3250/645/6450 As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to VCC. The lower limit is: The upper limit is: 1024 ⋅ 1.5V ⋅ 0,95 ⁄ 5V = 291 = 0x123 1024 ⋅ 1.5V ⋅ 1.05 ⁄ 5V = 323 = 0x143 The recommended values from Table 25-5 are used unless other values are given in the algorithm in Table 25-6. Only the DAC and port pin values of the Scan Chain are shown.
ATmega325/3250/645/6450 25.7 Boundary-scan Order Table 25-7 and Table 25-8 shows the Scan order between TDI and TDO when the Boundaryscan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports.
ATmega325/3250/645/6450 Table 25-7.
ATmega325/3250/645/6450 Table 25-7. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 157 PE0.Data Port E 156 PE0.Control 155 PE0.Pull-up_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pull-up_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pull-up_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pull-up_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pull-up_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pull-up_Enable 139 PE6.Data 138 PE6.
ATmega325/3250/645/6450 Table 25-7. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 133 PB0.Data Port B 132 PB0.Control 131 PB0.Pull-up_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pull-up_Enable 127 PB2.Data 126 PB2.Control 125 PB2.Pull-up_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pull-up_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pull-up_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pull-up_Enable 115 PB6.Data 114 PB6.
ATmega325/3250/645/6450 Table 25-7. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name Module 100 EXTCLKEN Enable signals for main Clock/Oscillators 99 OSCON 98 RCOSCEN 97 OSC32EN 96 EXTCLK (XTAL1) 95 OSCCK 94 RCCK 93 OSC32CK 92 PD0.Data 91 PD0.Control 90 PD0.Pull-up_Enable 89 PD1.Data 88 PD1.Control 87 PD1.Pull-up_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pull-up_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pull-up_Enable 80 PD4.
ATmega325/3250/645/6450 Table 25-7. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 64 PG1.Control 63 PG1.Pull-up_Enable 62 PC0.Data 61 PC0.Control 60 PC0.Pull-up_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pull-up_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pull-up_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pull-up_Enable 50 PC4.Data 49 PC4.Control 48 PC4.Pull-up_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pull-up_Enable 44 PC6.Data 43 PC6.
ATmega325/3250/645/6450 Table 25-7. ATmega325/645 Boundary-scan Order, 64-pin (Continued) Bit Number Signal Name 28 PA5.Control 27 PA5.Pull-up_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pull-up_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pull-up_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pull-up_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pull-up_Enable 14 PA0.Data 13 PA0.Control 12 PA0.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.
ATmega325/3250/645/6450 Table 25-8.
ATmega325/3250/645/6450 Table 25-8. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 207 NEGSEL_0 206 PASSEN 205 PRECH 204 ST 203 VCCREN 202 PE0.Data 201 PE0.Control 200 PE0.Pull-up_Enable 199 PE1.Data 198 PE1.Control 197 PE1.Pull-up_Enable 196 PE2.Data 195 PE2.Control 194 PE2.Pull-up_Enable 193 PE3.Data 192 PE3.Control 191 PE3.Pull-up_Enable 190 PE4.Data 189 PE4.Control 188 PE4.Pull-up_Enable 187 PE5.Data 186 PE5.
ATmega325/3250/645/6450 Table 25-8. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name Module 171 PB0.Control 170 PB0.Pull-up_Enable 169 PB1.Data 168 PB1.Control 167 PB1.Pull-up_Enable 166 PB2.Data 165 PB2.Control 164 PB2.Pull-up_Enable 163 PB3.Data 162 PB3.Control 161 PB3.Pull-up_Enable 160 PB4.Data 159 PB4.Control 158 PB4.Pull-up_Enable 157 PB5.Data 156 PB5.Control 155 PB5.Pull-up_Enable 154 PB6.Data 153 PB6.Control 152 PB6.
ATmega325/3250/645/6450 Table 25-8. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name Module 135 EXTCLK (XTAL1) 134 OSCCK Clock input and Oscillators for the main clock (Observe-only) 133 RCCK 132 OSC32CK 131 PJ2.Data 130 PJ2.Control 129 PJ2.Pull-up_Enable 128 PJ3.Data 127 PJ3.Control 126 PJ3.Pull-up_Enable 125 PJ4.Data 124 PJ4.Control 123 PJ4.Pull-up_Enable 122 PJ5.Data 121 PJ5.Control 120 PJ5.Pull-up_Enable 119 PJ6.Data 118 PJ6.
ATmega325/3250/645/6450 Table 25-8. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 99 PD5.Pull-up_Enable 98 PD6.Data 97 PD6.Control 96 PD6.Pull-up_Enable 95 PD7.Data 94 PD7.Control 93 PD7.Pull-up_Enable 92 PG0.Data 91 PG0.Control 90 PG0.Pull-up_Enable 89 PG1.Data 88 PG1.Control 87 PG1.Pull-up_Enable 86 PC0.Data 85 PC0.Control 84 PC0.Pull-up_Enable 83 PC1.Data 82 PC1.Control 81 PC1.Pull-up_Enable 80 PC2.Data 79 PC2.
ATmega325/3250/645/6450 Table 25-8. ATmega3250/6450 Boundary-scan Order, 100-pin (Continued) Bit Number Signal Name 63 PH1.Pull-up_Enable 62 PH2.Data 61 PH2.Control 60 PH2.Pull-up_Enable 59 PH3.Data 58 PH3.Control 57 PH3.Pull-up_Enable 56 PC6.Data 55 PC6.Control 54 PC6.Pull-up_Enable 53 PC7.Data 52 PC7.Control 51 PC7.Pull-up_Enable 50 PG2.Data 49 PG2.Control 48 PG2.Pull-up_Enable 47 PA7.Data 46 PA7.Control 45 PA7.Pull-up_Enable 44 PA6.Data 43 PA6.
ATmega325/3250/645/6450 Table 25-8. Bit Number Signal Name 27 PA1.Pull-up_Enable 26 PA0.Data 25 PA0.Control 24 PA0.Pull-up_Enable 23 PH4.Data 22 PH4.Control 21 PH4.Pull-up_Enable 20 PH5.Data 19 PH5.Control 18 PH5.Pull-up_Enable 17 PH6.Data 16 PH6.Control 15 PH6.Pull-up_Enable 14 PH7.Data 13 PH7.Control 12 PH7.Pull-up_Enable 11 PF3.Data 10 PF3.Control 9 PF3.Pull-up_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pull-up_Enable 5 PF1.Data 4 PF1.Control 3 PF1.
ATmega325/3250/645/6450 26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory Size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 26.2 1. A page is a section in the Flash consisting of several bytes (see Table 27-10 on page 270) used during programming.
ATmega325/3250/645/6450 26.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
ATmega325/3250/645/6450 Figure 26-1. Read-While-Write vs.
ATmega325/3250/645/6450 Figure 26-2.
ATmega325/3250/645/6450 Table 26-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 3 0 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
ATmega325/3250/645/6450 Note: 26.7 1. “1” means unprogrammed, “0” means programmed Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit 15 14 13 12 11 10 9 8 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 27-10 on page 270), the Program Counter can be treated as having two different sections.
ATmega325/3250/645/6450 26.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
ATmega325/3250/645/6450 • Page Write to the RWW section: The NRWW section can be read during the Page Write. • Page Write to the NRWW section: The CPU is halted during the operation. 26.8.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software.
ATmega325/3250/645/6450 26.8.9 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register.
ATmega325/3250/645/6450 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used.
ATmega325/3250/645/6450 brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<
ATmega325/3250/645/6450 26.8.13 Atmel ATmega325/3250/645/6450 Boot Loader Parameters In Table 26-6 through Table 26-8, the parameters used in the description of the Self-Programming are given. Table 26-6.
ATmega325/3250/645/6450 26.9 26.9.1 Register Description Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
ATmega325/3250/645/6450 will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored.
ATmega325/3250/645/6450 27. Memory Programming 27.1 Program And Data Memory Lock Bits The Atmel ATmega325/3250/645/6450 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1.
ATmega325/3250/645/6450 Lock Bit Protection Modes(1)(2) (Continued) Table 27-2. Memory Lock Bits Protection Type BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section.
ATmega325/3250/645/6450 Table 27-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN(1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
ATmega325/3250/645/6450 The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. 27.2.1 27.3 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed.
ATmega325/3250/645/6450 Figure 27-1. Parallel Programming +5V RDY/BSY PD1 OE PD2 WR PD3 BS1 PD4 XA0 PD5 XA1 PD6 PAGEL PD7 +12 V VCC +5V AVCC PB7 - PB0 DATA RESET BS2 PA0 XTAL1 GND Table 27-6. Pin Name Mapping Signal Name in Programming Mode Pin Name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low).
ATmega325/3250/645/6450 Table 27-8. XA1 and XA0 Coding XA1 XA0 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 27-9.
ATmega325/3250/645/6450 27.6 27.6.1 Parallel Programming Enter Programming Mode The following algorithm puts the device in Parallel (High-voltage) Programming mode: 1. Set Prog_enable pins listed in Table 27-7 on page 269 to “0000”, RESET pin and VCC to 0V. 2. Apply 4.5 - 5.5V between VCC and GND. 3. Ensure that VCC reaches at least 1.8V within the next 20 µs. 4. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET. 5.
ATmega325/3250/645/6450 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 27.6.4 Programming the Flash The Flash is organized in pages, see Table 27-10 on page 270.
ATmega325/3250/645/6450 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 27-3 for signal waveforms). I.
ATmega325/3250/645/6450 Figure 27-3. Programming the Flash Waveforms(1) F DATA A B 0x10 ADDR. LOW C DATA LOW D E DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G ADDR. HIGH H XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 27.6.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 27-11 on page 270.
ATmega325/3250/645/6450 Figure 27-4. Programming the EEPROM Waveforms K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 27.6.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 272 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3.
ATmega325/3250/645/6450 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 27.6.10 Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the Flash” on page 272 for details on Command and Data loading): 1.
ATmega325/3250/645/6450 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). 5. Set OE to “0”, BS2 to “0” and BS1 to “1”.
ATmega325/3250/645/6450 27.6.15 Parallel Programming Characteristics Figure 27-7. Parallel Programming Timing, Including some General Timing Requirements tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 27-8.
ATmega325/3250/645/6450 Figure 27-9. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE DATA tOHDZ ADDR0 (Low Byte) DATA (Low Byte) ADDR1 (Low Byte) DATA (High Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 27-7 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Table 27-12.
ATmega325/3250/645/6450 Table 27-12. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter tBVDV BS1 Valid to DATA valid tOLDV tOHDZ Notes: 27.7 Min Max Units 250 ns OE Low to DATA Valid 250 ns OE High to DATA Tri-stated 250 ns 0 Typ 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command.
ATmega325/3250/645/6450 Low: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz 27.7.2 Serial Programming Algorithm When writing serial data to the Atmel ATmega325/3250/645/6450, data is clocked on the rising edge of SCK. When reading data from the Atmel ATmega325/3250/645/6450, data is clocked on the falling edge of SCK. See Figure 27-11 for timing details.
ATmega325/3250/645/6450 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Table 27-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 4.5ms tWD_EEPROM 9.0ms tWD_ERASE 9.0ms Figure 27-11. Serial Programming Waveforms SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 27.7.
ATmega325/3250/645/6450 Table 27-15.
ATmega325/3250/645/6450 Figure 27-12. Serial Programming Instruction example Serial Programming Instruction Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Adr MSB A Bit 15 B Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 4 Byte 2 Adr LSB Adr MSB Bit 15 B 0 Byte 3 Byte 4 Adrr LSB B 0 Page Buffer Page Offset Page 0 Page 1 Page 2 Page Number Page N-1 Program Memory/ EEPROM Memory 27.7.4 27.
ATmega325/3250/645/6450 27.8.1 Programming Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks.
ATmega325/3250/645/6450 27.8.3 27.8.4 27.8.5 27.8.6 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16bit Programming Enable Register is selected as Data Register. The active states are the following: • Shift-DR: The programming enable signature is shifted into the Data Register. • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid.
ATmega325/3250/645/6450 27.8.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 285. The Data Registers relevant for programming operations are: • 27.8.8 Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register Reset Register The Reset Register is a Test Data Register used to reset the part during programming.
ATmega325/3250/645/6450 Figure 27-14.
ATmega325/3250/645/6450 Table 27-16. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
ATmega325/3250/645/6450 Table 27-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 0100011_01000000 xxxxxxx_xxxxxxxx 6b.
ATmega325/3250/645/6450 Table 27-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext.
ATmega325/3250/645/6450 Figure 27-15. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.8.
ATmega325/3250/645/6450 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 27-16.
ATmega325/3250/645/6450 27.8.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-12 on page 279). 27.8.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 294. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3.
ATmega325/3250/645/6450 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 27-10 on page 270) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash).
ATmega325/3250/645/6450 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-12 on page 279). 27.8.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5.
ATmega325/3250/645/6450 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.
ATmega325/3250/645/6450 Table 28-1. Symbol TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Parameter Power Supply Current ICC Power-down mode(5) Condition Max. Units Active 1MHz, VCC = 2V 0.55 mA Active 4MHz, VCC = 3V 2.5 mA Active 8MHz, VCC = 5V 9 mA Idle 1MHz, VCC = 2V 0.2 mA Idle 4MHz, VCC = 3V 0.85 mA Idle 8MHz, VCC = 5V 3 mA Typ. WDT enabled, VCC = 3V 7 15 µA WDT disabled, VCC = 3V 0.
ATmega325/3250/645/6450 28.3 Speed Grades Maximum frequency is dependent on VCC. As shown in Figure 28-1 on page 299 and Figure 282 on page 299, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 28-1. Maximum Frequency vs. VCC (4 - 8 MHz). 8 MHz 4 MHz Safe Operating Area 1.8V 2.7V 5.5V Figure 28-2. Maximum Frequency vs. VCC (8 - 16 MHz). 16 MHz 8 MHz Safe Operating Area 2.7V 4.5V 5.
ATmega325/3250/645/6450 28.4 28.4.1 Clock Characteristics Calibrated Internal Oscillator Accuracy Table 28-2. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0 MHz 3V 25°C ±10% User Calibration 7.3 - 8.1 MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40°C - 85°C ±1% Note: 1. Voltage range for ATmega325V/3250V/645V/6450V. 2. Voltage range for Atmel ATmega325/3250/645/6450. 28.4.2 External Clock Drive Waveforms Figure 28-3.
ATmega325/3250/645/6450 28.5 System and Reset Characteristics Table 28-4. Reset, Brown-out and Internal Voltage Reference Characteristics Symbol Parameter VPOT(1) Condition Min Typ Max Units Power-on Reset Threshold Voltage (rising) TA = -40°C to 85°C 0.7 1.0 1.4 V Power-on Reset Threshold Voltage (falling)(1) TA = -40°C to 85°C 0.05 0.9 1.3 V 0.01 4.5 V/ms 0.2VCC 0.
ATmega325/3250/645/6450 28.6 SPI Timing Characteristics See Figure 28-4 and Figure 28-5 for details. Table 28-6. SPI Timing Parameters Description Mode 1 SCK period Master See Table 19-5 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
ATmega325/3250/645/6450 Figure 28-5. SPI Interface Timing Requirements (Slave Mode) SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
ATmega325/3250/645/6450 28.7 ADC Table 28-7. Symbol ADC Characteristics Parameter Condition Min Typ Max Units Single Ended Conversion 10 Bits Differential Conversion 8 Bits Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 4.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 2 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode 4.
ATmega325/3250/645/6450 Table 28-7. Symbol ADC Characteristics Parameter Condition Min Typ Max Units 1.0 1.1 1.2 V VINT Internal Voltage Reference RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Note: 1.
ATmega325/3250/645/6450 29. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off.
ATmega325/3250/645/6450 Figure 29-2. Active Supply Current vs. Frequency (1 - 16MHz)) 16 5.5 V 14 5.0 V 12 4.5 V ICC (mA) 10 8 6 4.0 V 3.3 V 2.7 V 4 2 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 14 85°C 25°C -40°C 12 ICC (mA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1MHz) 2.5 85°C 2 25°C -40°C ICC (mA) 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-5. Active Supply Current vs. VCC (32kHz External Oscillator) 70 85 °C 60 25 °C -40 °C I CC (u A) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 29.2 Idle Supply Current Figure 29-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.4 5.5 V 0.35 5.0 V 0.3 4.5 V ICC (mA) 0.25 4.0 V 0.2 3.3 V 0.15 2.7 V 0.1 1.8 V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-7. Idle Supply Current vs. Frequency (1 - 16MHz) 6 5.5 V 5 5.0 V 4.5 V ICC (mA) 4 3 2 4.0 V 3.3 V 1 2.7 V 1.
ATmega325/3250/645/6450 Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 7 6 85°C 5 -40°C ICC (mA) 25°C 4 3 2 1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1MHz) 1 0.9 85°C 0.8 25°C 0.7 -40°C ICC (mA) 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-10. Idle Supply Current vs. VCC (32kHz External Oscillator) 35 85 °C 30 25 °C -40 °C ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register.
ATmega325/3250/645/6450 29.3.0.1 Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 29-2 shows that we need to add 8.5% for the USART0, 9% for the SPI, and 4.8% for the TIMER1 module. From Figure 29-6, we find that the idle current consumption is ~0.16mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and SPI enabled, gives: I CC total ≈ 0.16mA • ( 1 + 0.085 + 0.09 + 0.048 ) ≈ 0.
ATmega325/3250/645/6450 29.5 Power-save Supply Current Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 30 25 85°C 25°C ICC (uA) 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.6 Standby Supply Current Figure 29-14. Standby Supply Current vs. VCC (Low Power Crystal Oscillator) 180 6MHz Xtal 6MHz Res. 160 140 4MHz Res. 4MHz Xtal ICC (uA) 120 100 80 2MHz Xtal 2MHz Res. 60 455kHz Res. 1MHz Res. 40 20 32kHz Xtal 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 29.7 Pin Pull-up Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 160 85°C 140 120 25°C -40°C IIO (uA) 100 80 60 40 20 0 0 1 2 3 4 5 VIO (V) Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 90 80 25°C 85°C 70 -40°C IIO (uA) 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.
ATmega325/3250/645/6450 Figure 29-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) 60 50 85°C 25°C IOP (uA) 40 -40°C 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) Figure 29-18. Reset Pull-up Resistor Current vs.
ATmega325/3250/645/6450 Figure 29-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 70 60 -40°C 25°C IRESET (uA) 50 85°C 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VRESET (V) Figure 29-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 40 -40°C 35 25°C 30 IRESET (uA) 85°C 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 29.8 Pin Driver Strength Figure 29-21. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) 70 IOH (mA) 60 -40°C 50 25°C 40 85°C 30 20 10 0 0 1 2 3 4 5 6 VOH (V) Figure 29-22. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) 25 -40°C 25°C 20 IOH (mA) 85°C 15 10 5 0 0 0.5 1 1.5 2 2.
ATmega325/3250/645/6450 Figure 29-23. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) 8 -40°C 7 25°C 6 85°C IOH (mA) 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Figure 29-24. I/O Pin Source Current vs.
ATmega325/3250/645/6450 Figure 29-25. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V) 35 30 -40°C 25°C 25 IOH (mA) 85°C 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOH (V) Figure 29-26. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8V) 10 -40°C 9 25°C 8 85°C IOH (mA) 7 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 Figure 29-27. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) 50 -40°C IOL (mA) 45 40 25°C 35 85°C 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 29-28. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) 20 -40°C 18 16 25°C IOL (mA) 14 85°C 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 Figure 29-29. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) 7 -40°C 6 25°C IOL (mA) 5 85°C 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 29-30. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) 90 80 -40°C 70 25°C IOL (mA) 60 85°C 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 Figure 29-31. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V) 35 -40°C 30 25°C 25 IOL (mA) 85°C 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) Figure 29-32. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) 12 -40°C 10 25°C 85°C IOL (mA) 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
ATmega325/3250/645/6450 29.9 Pin Thresholds and hysteresis Figure 29-33. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 85°C 25°C -40°C 3 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-34. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 3 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-35. I/O Pin Input Hysteresis vs. VCC 0.6 -40°C 0.5 Input Hysteresis (V) 25°C 0.4 85°C 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-36. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 Threshold (V) 2 1.5 -40°C 25°C 1 85°C 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-37. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 85°C 25°C -40°C 2.5 Threshold (V) 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 4 4.5 5 5.5 VCC (V) Figure 29-38. Reset Input Pin Hysteresis vs. VCC 0.7 0.6 -40°C Input Hysteresis (V) 0.5 25°C 0.4 0.3 85°C 0.2 0.1 0 1.5 2 2.5 3 3.
ATmega325/3250/645/6450 29.10 BOD Thresholds and Analog Comparator Offset Figure 29-39. BOD Thresholds vs. Temperature (BOD Level is 4.3V) 4.6 4.5 Rising VCC Threshold (V) 4.4 4.3 Falling VCC 4.2 4.1 4 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 29-40. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 3 2.9 Rising VCC Threshol d ( V) 2.8 2.7 Falling VCC 2.6 2.5 2.
ATmega325/3250/645/6450 Figure 29-41. BOD Thresholds vs. Temperature (BOD Level is 1.8V) 1.95 Threshold (V) 1.9 Rising VCC 1.85 1.8 Falling VCC 1.75 1.7 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 29-42. Bandgap Voltage vs. VCC 1.076 1.075 Bandgap Voltage (V) 1.074 25°C 1.073 1.072 85°C 1.071 1.07 1.069 -40°C 1.068 1.5 2 2.5 3 3.5 4 4.
ATmega325/3250/645/6450 Figure 29-43. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) 0.007 85°C Comparator Offset Voltage (V) 0.006 0.005 25°C 0.004 0.003 -40°C 0.002 0.001 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Figure 29-44. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 0.0035 Comparator Offset Voltage (V) 0.003 0.0025 85°C 0.002 0.0015 25°C 0.001 0.0005 -40°C 0 0 0.5 1 1.5 2 2.
ATmega325/3250/645/6450 29.11 Internal Oscillator Speed Figure 29-45. Watchdog Oscillator Frequency vs. VCC 1300 1250 -40 °C 25 °C 85 °C F RC (kHz) 1200 1150 1100 1050 1000 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-46. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.6 8.4 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V F RC (M Hz) 8.2 8 7.8 7.6 7.4 7.
ATmega325/3250/645/6450 Figure 29-47. Calibrated 8MHz RC Oscillator Frequency vs. VCC CC 8.6 8.4 85 °C 8.2 F RC (MHz) 25 °C 8 -40 °C 7.8 7.6 7.4 7.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-48. Calibrated 8MHz RC Oscillator Frequency vs.
ATmega325/3250/645/6450 29.12 Current Consumption of Peripheral Units Figure 29-49. Brownout Detector Current vs. VCC 40 -40 °C 25 °C 85 °C 35 30 I CC (u A) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-50. ADC Current vs. VCC (AREF = AVCC) 350 -40°C 25°C 85°C 300 ICC (uA) 250 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-51. AREF External Reference Current vs. VCC 85°C 25°C -40°C 160 140 120 IAREF (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-52. 32kHZ TOSC Current vs. VCC (Watchdog Timer Disabled) 25 85°C 25°C 20 ICC (uA) 15 10 5 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-53. Watchdog Timer Current vs. VCC 16 85°C 25°C -40°C 14 12 ICC (uA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-54. Analog Comparator Current vs. VCC 120 100 -40°C 80 25°C ICC (uA) 85°C 60 40 20 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 Figure 29-55. Programming Current vs. VCC 20 -40 °C 18 ICC (mA) 16 14 25 °C 12 85 °C 10 8 6 4 2 0 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 29.13 Current Consumption in Reset and Reset Pulsewidth Figure 29-56. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 0.2 0.18 5.5 V 0.16 5.0 V 0.14 4.5 V ICC (mA) 0.12 4.0 V 0.1 3.3 V 0.08 0.06 2.7 V 0.04 1.8 V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
ATmega325/3250/645/6450 Figure 29-57. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) 3 5.5 V 2.5 5.0 V ICC (mA) 2 4.5 V 1.5 1 4.0 V 3.3 V 0.5 2.7 V 1.8 V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 29-58. Reset Pulse Width vs. VCC 2500 Pulsewidth (ns) 2000 1500 1000 500 85°C 25°C -40°C 0 1.5 2 2.5 3 3.5 4 4.5 5 5.
ATmega325/3250/645/6450 30. Register Summary Note: Registers with bold type only available in ATmega3250/6450.
ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0xC3) Reserved - - - - - - - - Page (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 181 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 180 182 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserve
ATmega325/3250/645/6450 Address Name (0x84) TCNT1L Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (0x83) Reserved - - - - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 126 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 125 123 Timer/Counter1 Low - - Page 127 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 200 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 217 (0x7D)
ATmega325/3250/645/6450 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x25 (0x45) Reserved - - - - - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 96 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 101/147 0x22 (0x42) EEARH - - - - - 0x21 (0x41) EEARL EEPROM Address Register Low 0x20 (0x40) EEDR EEPROM Data Register 0x1F (0x3F) EECR - - - - EERIE EEPROM Address Register High Page 22 22 22 EEMWE EEWE EERE
ATmega325/3250/645/6450 31.
ATmega325/3250/645/6450 Mnemonics Operands Description Operation Flags #Clocks BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND
ATmega325/3250/645/6450 Mnemonics Operands Description Operation Flags #Clocks IN Rd, P In Port Rd ← P None OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
ATmega325/3250/645/6450 32. Ordering Information 32.1 ATmega325 Speed (MHz)(3) 8 16 Notes: Ordering Code(2) Package Type(1) 1.8 - 5.5V ATmega325V-8AU ATmega325V-8AUR(4) ATmega325V-8MU ATmega325V-8MUR(4) 64A 64A 64M1 64M1 2.7 - 5.5V ATmega325-16AU ATmega325-16AUR(4) ATmega325-16MU ATmega325-16MUR(4) 64A 64A 64M1 64M1 Power Supply Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
ATmega325/3250/645/6450 32.2 ATmega3250 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code(2) Package Type(1) 1.8 - 5.5V ATmega3250V-8AU ATmega3250V-8AUR(4) 100A 100A 2.7 - 5.5V ATmega3250-16AU ATmega3250-16AUR(4) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega325/3250/645/6450 32.3 ATmega645 Speed (MHz)(3) 8 16 Notes: Ordering Code(2) Package Type(1) 1.8 - 5.5V ATmega645V-8AU ATmega645V-8AUR(4) ATmega645V-8MU ATmega645V-8MUR(4) 64A 64A 64M1 64M1 2.7 - 5.5V ATmega645-16AU ATmega645-16AUR(4) ATmega645-16MU ATmega645-16MUR(4) 64A 64A 64M1 64M1 Power Supply Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form.
ATmega325/3250/645/6450 32.4 ATmega6450 Speed (MHz)(3) Power Supply 8 16 Notes: Ordering Code(2) Package Type(1) 1.8 - 5.5V ATmega6450V-8AU ATmega6450V-8AUR(4) 100A 100A 2.7 - 5.5V ATmega6450-16AU ATmega6450-16AUR(4) 100A 100A Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
ATmega325/3250/645/6450 33. Packaging Information 33.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.
ATmega325/3250/645/6450 33.2 64M1 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A K 0.08 C L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 – 0.02 0.05 0.18 0.25 0.30 A1 b K Option C b e BOTTOM VIEW Notes: Pin #1 Notch (0.20 R) D 8.90 9.00 9.10 D2 5.20 5.40 5.60 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e NOTE 0.50 BSC L 0.
ATmega325/3250/645/6450 33.3 100A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
ATmega325/3250/645/6450 34. Errata 34.1 Errata ATmega325 The revision letter in this section refers to the revision of the ATmega325 device. 34.1.1 ATmega325 Rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega325/3250/645/6450 34.2.3 ATmega3250 Rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00.
ATmega325/3250/645/6450 35. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision. 35.1 Rev. 2570N – 05/11 1. 2. 35.2 Rev. 2570M – 04/11 1. 2. 3. 4. 5. 6. 35.3 Updated “Features” on page 1. Added “Data Retention” on page 9 Updated “Serial Programming Algorithm” on page 281. Updated “Speed Grades” on page 299.
ATmega325/3250/645/6450 35.6 Rev. 2570I – 07/06 1. 2. 3. 4. 5. 6. 35.7 Rev. 2570H – 06/06 1. 2. 3. 35.8 Updated “Calibrated Internal RC Oscillator” on page 29. Updated “OSCCAL – Oscillator Calibration Register” on page 32. Added Table 28-2 on page 300. Rev. 2570G – 04/06 1. 35.9 Updated Table 15-6 on page 92. Updated Table 15-2 on page 97, Table 15-4 on page 97, Table 17-3 on page 124, Table 17-5 on page 125, Table 18-2 on page 143 and Table 18-4 on page 144. Updated “Fast PWM Mode” on page 115.
ATmega325/3250/645/6450 35.11 Rev. 2570D – 05/05 1. 2. 3. 4. 5. 6. 7. 8. 9. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. Added “Pin Change Interrupt Timing” on page 55. Updated “Signature Bytes” on page 268. Updated Table 27-15 on page 282. Added Figure 27-12 on page 284. Updated Figure 23-9 on page 209 and Figure 27-5 on page 276. Updated algorithm “Enter Programming Mode” on page 271. Added “Supply Current of I/O modules” on page 311.
ATmega325/3250/645/6450 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 2.1 Block Diagram ...................................................................................................4 2.
ATmega325/3250/645/6450 9.6 External Clock .................................................................................................30 9.7 Clock Output Buffer .........................................................................................31 9.8 Timer/Counter Oscillator ..................................................................................31 9.9 System Clock Prescaler ..................................................................................32 9.
ATmega325/3250/645/6450 14.1 Overview ..........................................................................................................60 14.2 Ports as General Digital I/O .............................................................................61 14.3 Alternate Port Functions ..................................................................................66 14.4 Register Description ........................................................................................
ATmega325/3250/645/6450 18.7 Modes of Operation .......................................................................................135 18.8 Timer/Counter Timing Diagrams ...................................................................139 18.9 Asynchronous Operation of Timer/Counter2 .................................................141 18.10 Timer/Counter Prescaler ...............................................................................142 18.11 Register Description ...................
ATmega325/3250/645/6450 23.3 Starting a Conversion ....................................................................................203 23.4 Prescaling and Conversion Timing ................................................................204 23.5 Changing Channel or Reference Selection ...................................................206 23.6 ADC Noise Canceler .....................................................................................207 23.7 ADC Conversion Result ..................
ATmega325/3250/645/6450 26.9 Register Description ......................................................................................263 27 Memory Programming ......................................................................... 265 27.1 Program And Data Memory Lock Bits ...........................................................265 27.2 Fuse Bits ........................................................................................................266 27.3 Signature Bytes ...................
ATmega325/3250/645/6450 32 Ordering Information ........................................................................... 343 32.1 ATmega325 ...................................................................................................343 32.2 ATmega3250 .................................................................................................344 32.3 ATmega645 ...................................................................................................345 32.4 ATmega6450 ........
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