Datasheet

8011N–AVR–01/10

ATmega164P/324P/644P

The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the

1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible

through all these addressing modes. The Register File is described in ”General Purpose Regis-

ter File” on page 12.

Figure 5-2. Data Memory Map for ATmega164P/324P/644P.

5.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

32 Registers

64 I/O Registers

Internal SRAM

(1024/2048/4096 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x04FF/0x08FF/0x10FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction