Datasheet

161

8011N–AVR–01/10

ATmega164P/324P/644P

15. SPI – Serial Peripheral Interface

15.1 Features

• Full-duplex, Three-wire Synchronous Data Transfer

• Master or Slave Operation

• LSB First or MSB First Data Transfer

• Seven Programmable Bit Rates

• End of Transmission Interrupt Flag

• Write Collision Flag Protection

• Wake-up from Idle Mode

• Double Speed (CK/2) Master SPI Mode

15.2 Overview

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

ATmega164P/324P/644P and peripheral devices or between several AVR devices.

USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 198.

The Power Reduction SPI bit, PRSPI, in ”PRR – Power Reduction Register” on page 48 on page

50 must be written to zero to enable SPI module.

Figure 15-1. SPI Block Diagram

(1)

Note: 1. Refer to Figure 1-1 on page 2, and Table 11-6 on page 82 for SPI pin placement.

SPI2X

DIVIDER

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