Datasheet

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

• Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt 2 - 0 Sense Control Bits

The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 13-1. Edges on INT2:INT0 are registered asynchro-

nously. Pulses on INT2:0 pins wider than the minimum pulse width given in ”External interrupts

characteristics” on page 338 will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until the com-

pletion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low. When changing the

ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its

Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn

interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the

EIFR Register before the interrupt is re-enabled.

Note: 1. n = 2, 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

13.2.2 EIMSK – External Interrupt Mask Register

• Bits 2:0 – INT2:0: External Interrupt Request 2 - 0 Enable

When an INT2:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the

corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External

Interrupt Control Register, EICRA, defines whether the external interrupt is activated on rising or

falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if

the pin is enabled as an output. This provides a way of generating a software interrupt.

13.2.3 EIFR –External Interrupt Flag Register

• Bits 2:0 – INTF2:0: External Interrupt Flags 2 - 0

When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

Table 13-1. Interrupt Sense Control

(1)

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request

0 1 Any edge of INTn generates asynchronously an interrupt request

1 0 The falling edge of INTn generates asynchronously an interrupt request

1 1 The rising edge of INTn generates asynchronously an interrupt request

Bit 76543210

0x1D (0x3D)

– – – – – INT2 INT1 IINT0 EIMSK

Read/Write RRRRRR/WR/WR/W

Initial Value00000000

Bit 76543210

0x1C (0x3C)

– – – – – INTF2 INTF1 IINTF0 EIFR

Read/WriteR/WRRRRR/WR/WR/W

Initial Value00000000