Datasheet

v
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
21 Two-wire Serial Interface ..................................................................... 211
21.1Features ..............................................................................................................211
21.2Two-wire Serial Interface bus definition ...............................................................211
21.3Data Transfer and Frame Format ........................................................................212
21.4Multi-master Bus Systems, Arbitration and Synchronization ...............................215
21.5Overview of the TWI Module ...............................................................................217
21.6Using the TWI ......................................................................................................219
21.7Transmission modes ...........................................................................................222
21.8Multi-master Systems and Arbitration ..................................................................235
21.9Register description .............................................................................................236
22 AC - Analog Comparator ..................................................................... 241
22.1Overview .............................................................................................................241
22.2Analog Comparator Multiplexed Input .................................................................241
22.3Register description .............................................................................................242
23 ADC - Analog-to-digital converter ...................................................... 244
23.1Features ..............................................................................................................244
23.2Overview .............................................................................................................244
23.3Operation .............................................................................................................245
23.4Starting a conversion ...........................................................................................246
23.5Prescaling and Conversion Timing ......................................................................247
23.6Changing Channel or Reference Selection .........................................................250
23.7ADC Noise Canceler ...........................................................................................252
23.8ADC Conversion Result ......................................................................................257
23.9Register description .............................................................................................259
24 JTAG interface and on-chip debug system ....................................... 264
24.1Features ..............................................................................................................264
24.2Overview .............................................................................................................264
24.3TAP – Test Access Port ......................................................................................264
24.4TAP controller ......................................................................................................266
24.5Using the Boundary-scan Chain ..........................................................................267
24.6Using the On-chip Debug System .......................................................................267
24.7On-chip Debug Specific JTAG Instructions .........................................................268
24.8Using the JTAG Programming Capabilities .........................................................268
24.9Bibliography .........................................................................................................269
24.10Register description ...........................................................................................269