Datasheet

312
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Figure 27-7. Parallel programming timing, including some general timing requirements.
Figure 27-8. Parallel programming timing, loading sequence with timing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 27-7 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
loading operation.
Figure 27-9. Parallel programming timing, reading sequence (within the same page) with tim-
ing requirements
(1)
.
Note: 1. The timing requirements shown in Figure 27-7 (that is, t
DVXH
, t
XHXL
, and t
XLDX
) also apply to
reading operation.
Data & Contol
(DATA, XA0/1, BS1, BS2)
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
XTAL1
PAGEL
t
PLXH
XLXH
t
t
XLPH
ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
OE
ADDR0 (Low Byte) DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZ