Datasheet

175
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
19. USART
19.1 Features
• Full duplex operation (independent serial receive and transmit registers)
• Asynchronous or synchronous operation
• Master or Slave clocked synchronous operation
• High resolution baud rate generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
• Odd or even parity generation and parity check supported by hardware
• Data OverRun detection
• Framing Error detection
• Noise filtering includes False Start bit detection and Digital Low Pass Filter
• Three separate interrupts on TX complete, TX Data Register Empty and RX Complete
• Multi-processor Communication mode
• Double Speed Asynchronous Communication mode
19.2 USART1 and USART0
The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has two USART’s,
USART0 and USART1.
The functionality for all USART’s is described below, most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the USART number.
USART0 and USART1 have different I/O registers as shown in ”Register summary” on page
554.
19.3 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
A simplified block diagram of the USART Transmitter is shown in Figure 19-1 on page 176. CPU
accessible I/O Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in ”PRR0 – Power Reduction Register 0” on
page 48 must be disabled by writing a logical zero to it.
The Power Reducion USART1 bit, PRUSART1, in ”PRR1 – Power Reduction Register 1” on
page 49 must be disabled by writing a logical zero to it.