Datasheet

165
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
18. SPI – Serial Peripheral Interface
18.1 Features
• Full-duplex, three-wire synchronous data transfer
• Master or Slave operation
• LSB first or MSB first data transfer
• Seven programmable bit rates
• End of Transmission Interrupt flag
• Write Collision flag protection
• Wake-up from Idle mode
• Double speed (CK/2) Master SPI mode
18.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P and peripheral devices or
between several AVR devices.
USART can also be used in Master SPI mode, see ”USART in SPI mode” on page 202.
The Power Reduction SPI bit, PRSPI, in ”PRR0 – Power Reduction Register 0” on page 48 must
be written to zero to enable SPI module.
Figure 18-1. SPI block diagram
(1)
.
Note: 1. Refer to Figure 1-1 on page 2, and Table 14-6 on page 82 for SPI pin placement.
SPI2X
SPI2X
DIVIDER
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