Datasheet

143
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
17. 8-bit Timer/Counter2 with PWM and asynchronous operation
17.1 Features
• Single channel counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, phase correct Pulse Width Modulator (PWM)
• Frequency generator
• 10-bit clock prescaler
• Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
• Allows clocking from external 32kHz watch crystal independent of the I/O clock
17.2 Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-12.. For the actual
placement of I/O pins, see ”Pin configurations” on page 2. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the ”Register description” on page 157.
The Power Reduction Timer/Counter2 bit, PRTIM2, in ”PRR0 – Power Reduction Register 0” on
page 48 must be written to zero to enable Timer/Counter2 module.
Figure 17-1. 8-bit Timer/Counter block diagram.
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
=
Fixed
TOP
Value
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
clk
Tn
ASSRn
Synchronization Unit
Prescaler
T/C
Oscillator
clk
I/O
clk
ASY
asynchronous mode
select (ASn)
Synchronized Status flags
TOSC1
TOSC2
Status flags
clk
I/O