Datasheet

133
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Figure 16-13. Timer/Counter Timing diagram, with prescaler (f
clk_I/O
/8).
16.12 Register description
16.12.1 TCCRnA – Timer/Counter n Control Register A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting. Table 16-2 on page 133 shows the COMnx1:0 bit functionality
when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit 7 6 5 4 3210
(0x80)
COMnA1 COMnA0 COMnB1 COMnB0
– –
WGMn1 WGMn0 TCCRnA
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value0 0 0 0 0000
Table 16-2. Compare Output mode, non-PWM.
COMnA1/COMnB1 COMnA0/COMnB0 Description
0 0 Normal port operation, OCnA/OCnB disconnected.
0 1 Toggle OCnA/OCnB on Compare Match.
10
Clear OCnA/OCnB on Compare Match (Set output to
low level).
11
Set OCnA/OCnB on Compare Match (Set output to
high level).