Datasheet

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Features

• High-performance, low-power 8-bit Atmel

AVR

Microcontroller

• Advanced RISC architecture

– 131 powerful Instructions – most single-clock cycle execution

– 32 × 8 general purpose working registers

– Fully static operation

– Up to 20MIPS throughput at 20MHz

– On-chip 2-cycle multiplier

• High endurance non-volatile memory segments

– 16/32/64/128KBytes of In-System Self-programmable Flash program memory

– 512/1K/2K/4KBytes EEPROM

– 1/2/4/16KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C

(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• Atmel QTouch

library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix acquisition

– Up to 64 sense channels

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One/two 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1×, 10× or 200×

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

• Operating Voltages

– 1.8 - 5.5V

• Speed Grades

– 0 - 4MHz @ 1.8 - 5.5V

– 0 - 10MHz @ 2.7 - 5.5V

– 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1MHz, 1.8V, 25C

– Active: 0.4mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32kHz RTC)

Note: 1. See ”Data retention” on page 9 for details.

8-bit Atmel

Microcontroller

with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164A

ATmega164PA

ATmega324A

ATmega324PA

ATmega644A

ATmega644PA

ATmega1284

ATmega1284P

8272E–AVR–04/2013

Summary of content (586 pages)

PAGE 1
Features • High-performance, low-power 8-bit Atmel® AVR® Microcontroller • Advanced RISC architecture • • • • • • • • • – 131 powerful Instructions – most single-clock cycle execution – 32 × 8 general purpose working registers – Fully static operation – Up to 20MIPS throughput at 20MHz – On-chip 2-cycle multiplier High endurance non-volatile memory segments – 16/32/64/128KBytes of In-System Self-programmable Flash program memory – 512/1K/2K/4KBytes EEPROM – 1/2/4/16KBytes Internal SRAM – Write/Eras
PAGE 2
ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Pin configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Figure 1-1. Pinout.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 1.2 Pinout - DRQFN for Atmel ATmega164A/164PA/324A/324PA Figure 1-2. DRQFN - pinout. Top view Bottom view A24 B20 A23 B19 A22 B18 A21 B17 A20 B16 A19 A19 B16 A20 B17 A21 B18 A22 B19 A23 B20 A24 A1 A18 B1 B15 A17 B2 B14 B3 B4 A2 A3 A4 Table 1-1.
PAGE 4
ATmega164A/PA/324A/PA/644A/PA/1284/P 1.3 Pinout - VFBGA for Atmel ATmega164A/164PA/324A/324PA Figure 1-3. VFBGA - pinout. Top view 1 2 3 4 5 Bottom view 6 7 7 6 5 4 3 2 1 A A B B C C D D E E F F G G Table 1-2. BGA - pinout.
PAGE 5
ATmega164A/PA/324A/PA/644A/PA/1284/P 2. Overview The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block diagram Figure 2-1. Block diagram. PA7..0 PB7..
PAGE 6
ATmega164A/PA/324A/PA/644A/PA/1284/P The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provide the following features: 16/32/64/128Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K/4Kbytes EEPROM, 1/2/4/16Kbytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three (four for ATmega1284/1284P) flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented two-wire Serial Interface, a 8-channel, 10-b
PAGE 7
ATmega164A/PA/324A/PA/644A/PA/1284/P 2.2 Comparison between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P Table 2-1. Differences between ATmega164A, ATmega164PA, ATmega324A, ATmega324PA, ATmega644A, ATmega644PA, ATmega1284 and ATmega1284P.
PAGE 8
ATmega164A/PA/324A/PA/644A/PA/1284/P capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of the JTAG interface, along with special features of the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P as listed on page 85. 2.3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 3. Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 4. About code examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
PAGE 10
ATmega164A/PA/324A/PA/644A/PA/1284/P 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1. Block diagram of the AVR architecture.
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ATmega164A/PA/324A/PA/644A/PA/1284/P ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory.
PAGE 12
ATmega164A/PA/324A/PA/644A/PA/1284/P specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set.
PAGE 14
ATmega164A/PA/324A/PA/644A/PA/1284/P 7.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 7.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write Initial Value Note: R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0/0(1) 0/1(1) 1/0(1) 0 0 1 1 1 1 1 1 1 1 1.
PAGE 16
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 7-5. The Parallel Instruction Fetches and Instruction Executions. T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
PAGE 17
ATmega164A/PA/324A/PA/644A/PA/1284/P interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 7.7.1 Interrupt response time The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum.
PAGE 19
ATmega164A/PA/324A/PA/644A/PA/1284/P 8. AVR memories 8.1 Overview This section describes the different memories in the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 8-1. Program memory map. Program Memory 0x0000 Application Flash Section Boot Flash Section 0x1FFF/0x3FFF/0x7FFF/0xFFFF 8.3 SRAM data memory Figure 8-2 shows how the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P SRAM Memory is organized. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
PAGE 21
ATmega164A/PA/324A/PA/644A/PA/1284/P The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P are all accessible through all these addressing modes. The Register File is described in ”General Purpose Register File” on page 13. Figure 8-2. Data Memory Map for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P.
PAGE 22
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.4 EEPROM data memory The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains 512/1K/2K/4Kbytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
PAGE 23
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.5 I/O memory The I/O space definition of the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is shown in ”Register summary” on page 554. All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space.
PAGE 24
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.6 8.6.
PAGE 25
ATmega164A/PA/324A/PA/644A/PA/1284/P operations. The Programming times for the different modes are shown in Table 8-1 on page 25. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 8-1. EEPROM Mode Bits. EEPM1 EEPM0 Programming time 0 0 3.4ms Erase and Write in one operation (Atomic Operation) 0 1 1.8ms Erase Only 1 0 1.
PAGE 26
ATmega164A/PA/324A/PA/644A/PA/1284/P When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM.
PAGE 27
ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.
PAGE 28
ATmega164A/PA/324A/PA/644A/PA/1284/P The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
PAGE 29
ATmega164A/PA/324A/PA/644A/PA/1284/P 8.6.4 GPIOR2 – General Purpose I/O Register 2 Bit 8.6.5 7 5 4 3 2 1 0 MSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 LSB 5 4 3 2 1 GPIOR2 GPIOR1 – General Purpose I/O Register 1 Bit 8.6.
PAGE 30
ATmega164A/PA/324A/PA/644A/PA/1284/P 9. System clock and clock options 9.1 Clock systems and their distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ”Power management and sleep modes” on page 42. The clock systems are detailed below. Figure 9-1. Clock distribution.
PAGE 31
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.1.3 Flash Clock – clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock. 9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 9.1.
PAGE 32
ATmega164A/PA/324A/PA/644A/PA/1284/P selectable delays are shown in Table 9-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical characteristics” on page 345. Table 9-2. Number of Watchdog Oscillator Cycles. Typical time-out (VCC = 5.0V) Typical time-out (VCC = 3.0V) Number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8K (8,192) Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc.
PAGE 33
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.3 Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the ”Full swing Crystal Oscillator” on page 34. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3.
PAGE 34
ATmega164A/PA/324A/PA/644A/PA/1284/P Notes: 9.4 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up.
PAGE 35
ATmega164A/PA/324A/PA/644A/PA/1284/P 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application. 9.5 Low Frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use with a 32.768kHz watch crystal.
PAGE 36
ATmega164A/PA/324A/PA/644A/PA/1284/P To find suitable load capacitance for a 32.768kHz crysal, please consult the crystal datasheet. When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in Table 9-9. Table 9-9. Start-up times for the Low Frequency Crystal Oscillator Clock Selection. Power conditions Start-up time from power-down and power-save Additional delay from reset (VCC = 5.0V) 14CK (1) SUT1..
PAGE 37
ATmega164A/PA/324A/PA/644A/PA/1284/P When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 9-11 on page 37. Table 9-11. Start-up times for the Internal Calibrated RC Oscillator clock selection. Start-up time from powerdown and power-save Additional delay from reset (VCC = 5.0V) SUT1..0 BOD enabled 6CK 14CK 00 Fast rising power 6CK 14CK + 4.1ms 01 Slowly rising power 6CK 14CK + 65ms 10(1) Power conditions Reserved Note: 9.7 11 1.
PAGE 38
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.8 External clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 9-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 9-4. External clock drive configuration. NC XTAL2 EXTERNAL CLOCK SIGNAL XTAL1 GND When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 9-15. Table 9-14. Table 9-15. Crystal oscillator clock frequency.
PAGE 39
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.9 Timer/Counter Oscillator Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P uses the same type of crystal oscillator for Low-frequency Crystal Oscillator and Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 35 for details on the oscillator and crystal requirements. The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a external clock source. See ”Clock source connections” on page 32 for details.
PAGE 40
ATmega164A/PA/324A/PA/644A/PA/1284/P 9.12 9.12.1 Register description OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency.
PAGE 41
ATmega164A/PA/324A/PA/644A/PA/1284/P The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions.
PAGE 42
ATmega164A/PA/324A/PA/644A/PA/1284/P 10. Power management and sleep modes 10.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
PAGE 43
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.3 BOD disable(1) When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 27-3 on page 299, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 10-1 on page 42. The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses.
PAGE 44
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.6 Power-down mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the two-wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, two-wire Serial Interface address match, an external interrupt on INT2:0, or a pin change interrupt can wake up the MCU.
PAGE 45
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.10 Power Reduction Register The Power Reduction Register(PRR), see ”PRR0 – Power Reduction Register 0” on page 48, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock.
PAGE 46
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.11.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Watchdog Timer” on page 55 for details on how to configure the Watchdog Timer. 10.11.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 10.12 Register description 10.12.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 0x33 (0x53) – – – – SM2 SM1 SM0 SE Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SMCR • Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 10-2. Table 10-2.
PAGE 48
ATmega164A/PA/324A/PA/644A/PA/1284/P 10.12.2 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the Atmel ATmega164PA/324PA/644PA/1284P. • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 10-1 on page 42.
PAGE 49
ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.
PAGE 50
ATmega164A/PA/324A/PA/644A/PA/1284/P 11. System Control and Reset 11.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
PAGE 51
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 11-1. Reset logic. DATA BUS PORF BORF EXTRF WDRF JTRF MCU Status Register (MCUSR) Power-on Reset Circuit Brown-out Reset Circuit BODLEVEL [2..0] Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.1.2 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”” on page 337.
PAGE 52
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 11-2. MCU Start-up, RESET Tied to VCC. VCC RESET VPOT VRST tTOUT TIME-OUT INTERNAL RESET Figure 11-3. MCU Start-up, RESET Extended Externally. VCC RESET VPOT VRST TIME-OUT tTOUT INTERNAL RESET 11.1.3 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see ”” on page 337) will generate a reset, even if the clock is not running.
PAGE 53
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.1.4 Brown-out Detection ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.
PAGE 54
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.2 Internal Voltage Reference ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 11.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in ”” on page 337.
PAGE 55
ATmega164A/PA/324A/PA/644A/PA/1284/P 11.3 11.3.1 Watchdog Timer Features • Clocked from separate On-chip Oscillator • Three operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 11.3.2 Overview Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128kHz oscillator.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watchdog Timer.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 2. In the example code IN and OUT instruction is used for access the I/O memory space above the IN and OUT address limit (IN and OUT limit is 0x00 to 0x3F). Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 11.4 11.4.1 Register description MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 11.4.2 WDTCSR – Watchdog Timer Control Register Bit 7 6 5 4 3 2 1 0 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X 0 0 0 WDTCSR • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 11-2 on page 60. . Table 11-2. Watchdog Timer Prescale Select. WDP3 WDP2 WDP1 WDP0 Number of WDT oscillator cycles Typical time-out at VCC = 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 12. Interrupts 12.1 Overview This section describes the specifics of the interrupt handling as performed in Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For a general explanation of the AVR interrupt handling, refer to ”Reset and interrupt handling” on page 16. 12.2 Interrupt Vectors in ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Table 12-1. Vector no. Reset and Interrupt Vectors.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 12-1. Vector no. Reset and Interrupt Vectors.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The most typical and general program setup for the Reset and Interrupt Vector Addresses in Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is: Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C 0x003E 0x0040 0x0042 0x0044 ; 0x003E 0x003F Labels RESET: 0x0040 0x0041 0x0042 0x0043 ... ...
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ATmega164A/PA/324A/PA/644A/PA/1284/P Notes: 1. Applies only to Atmel ATmega1284P.
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ATmega164A/PA/324A/PA/644A/PA/1284/P ... ... ... ; 0x1F036 jmp SPM_RDY ; SPM Ready Handler ; 12.2.1 0x1F03E RESET: ldi r16,high(RAMEND); Main program start 0x1F03F out SPH,r16 0x1F040 ldi r16,low(RAMEND) 0x1F041 0x1F042 out sei SPL,r16 0x1FO43 ; Set Stack Pointer to top of RAM ; Enable interrupts xxx Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 12.3 12.3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P 13. External Interrupts 13.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt 2 - 0 Sense Control Bits The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 13-1. Edges on INT2:INT0 are registered asynchronously.
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ATmega164A/PA/324A/PA/644A/PA/1284/P is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT2:0 are configured as level interrupt. Note that when entering sleep mode with the INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF2:0 flags. See ”Digital Input Enable and Sleep Modes” on page 76 for more information. 13.2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8 Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 13.2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14. I/O-Ports 14.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General digital I/O (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 14.2.2 Toggling the pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 14.2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 14-3. Synchronization when reading an externally applied pin value. SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max t pd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode, and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 14-5. Alternate port functions (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 14-2. Generic description of overriding signals for alternate functions. Signal name Full name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.1 Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 14-3. Table 14-3. Port pin Port A pins alternate functions.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-4 on page 81 and Table 14-5 on page 81 relate the alternate functions of Port A to the overriding signals shown in Figure 14-5 on page 78. Table 14-4. Overriding Signals for Alternate Functions in PA7:PA4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 14-6. Table 14-6. Port Pin Port B pins alternate functions.
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ATmega164A/PA/324A/PA/644A/PA/1284/P OC3A, Output Compare Match A output: The PB6 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB6 set “one”) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. PCINT14, Pin Change Interrupt source 14: The PB6 pin can serve as an external interrupt source. • MOSI/ICP3/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel.
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ATmega164A/PA/324A/PA/644A/PA/1284/P CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset. PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source. • T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-8. 14.3.3 Overriding Signals for Alternate Functions in PB3:PB0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • TOSC1/PCINT22 – Port C, Bit 6 TOSC1, Timer Oscillator pin 1. The PC6 pin can serve as an external interrupt source to the MCU. PCINT22, Pin Change Interrupt source 22: The PC6 pin can serve as an external interrupt source. • TDI/PCINT21 – Port C, Bit 5 TDI, JTAG Test Data Input. PCINT21, Pin Change Interrupt source 21: The PC5 pin can serve as an external interrupt source. • TDO/PCINT20 – Port C, Bit 4 TDO, JTAG Test Data Output.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 14-10. Overriding Signals for Alternate Functions in PC7:PC4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 14-12. Table 14-12. Port D pins alternate functions.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • OC1A/PCINT29 – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT29, Pin Change Interrupt Source 29: The PD5 pin can serve as an external interrupt source.
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ATmega164A/PA/324A/PA/644A/PA/1284/P PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt source. Table 14-13 on page 90 and Table 14-14 on page 90 relate the alternate functions of Port D to the overriding signals shown in Figure 14-5 on page 78. Table 14-13. Overriding Signals for Alternate Functions PD7:PD4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Register description 14.3.5 MCUCR – MCU Control Register Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the Atmel ATmega164PA/324PA/644PA/1284P.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 14.3.12 PORTC – Port C Data Register Bit 14.3.13 7 6 5 4 3 2 1 0 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRC – Port C Data Direction Register Bit 14.3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.
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ATmega164A/PA/324A/PA/644A/PA/1284/P uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B).
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ATmega164A/PA/324A/PA/644A/PA/1284/P count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clkTn Timer/Counter clock, referred to as clkT0 in the following. top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT0).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-3. Output Compare unit, block diagram. DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
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ATmega164A/PA/324A/PA/644A/PA/1284/P generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 15.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 104.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-5. CTC mode, timing diagram. OCnx Interrupt Flag Set TCNTn OCn (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
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ATmega164A/PA/324A/PA/644A/PA/1284/P PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0. Figure 15-6. Fast PWM mode, timing diagram.
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ATmega164A/PA/324A/PA/644A/PA/1284/P feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 15.7.4 Phase Correct PWM mode The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
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ATmega164A/PA/324A/PA/644A/PA/1284/P one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 15-4 on page 105). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 15-9. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM mode, where OCR0A is TOP. Figure 15-10. Timer/Counter Timing diagram, setting of OCF0x, with prescaler (fclk_I/O/8).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 15.9 15.9.1 Register description TCCR0A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 0x24 (0x44) COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0A • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-4. Compare Output mode, Phase Correct PWM mode (1). COM0A1 COM0A0 0 0 Normal port operation, OC0A disconnected. 0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected. WGM02 = 1: Toggle OC0A on Compare Match. 1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare Match when down-counting. 1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare Match when down-counting. Note: Description 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-7 on page 106 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. Compare Output mode, Phase Correct PWM mode (1). Table 15-7. COM0B1 COM0B0 0 0 Normal port operation, OC0B disconnected. 0 1 Reserved 1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare Match when down-counting. 1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare Match when down-counting.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 15.9.2 TCCR0B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 0x25 (0x45) FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TCCR0B • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 15-9. Clock Select bit description. CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register Bit 7 6 5 4 3 2 1 0 (0x6E) – – – – – OCIE0B OCIE0A TOIE0 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIMSK0 • Bits 7:3 – Reserved These bits are reserved and will always read as zero.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16. 16-bit Timer/Counter1 and Timer/Counter3(1) with PWM Note: 16.1 Features • • • • • • • • • • • 16.2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-1. 16-bit Timer/Counter block diagram (Note:). Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATA BUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 16.2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P See Section “16.8” on page 120. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See Section “22.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Examples (1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH ... C Code Examples (1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16.5 Prescaler Reset The prescaler is free running, that is, operates independently of the clock select logic of the Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clkTn is present or not.
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ATmega164A/PA/324A/PA/644A/PA/1284/P (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (ICIEn = 1), the Input Capture Flag generates an Input Capture interrupt. The ICFn Flag is automatically cleared when the interrupt is executed. Alternatively the ICFn Flag can be cleared by software by writing a logical one to its I/O bit location.
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ATmega164A/PA/324A/PA/644A/PA/1284/P not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt handler routine as possible.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-4. Output Compare unit, block diagram. DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16.8.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 16.8.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16.9 Compare Match Output unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16.9.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 133.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 16-6. CTC mode, timing diagram.
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ATmega164A/PA/324A/PA/644A/PA/1284/P rect and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA.
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ATmega164A/PA/324A/PA/644A/PA/1284/P value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered.
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ATmega164A/PA/324A/PA/644A/PA/1284/P operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX).
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ATmega164A/PA/324A/PA/644A/PA/1284/P OCRnx Registers are written. As the third period shown in Figure 16-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Register. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP.
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ATmega164A/PA/324A/PA/644A/PA/1284/P the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log  TOP + 1  R PFCPWM = ----------------------------------log  2  In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-11. Timer/Counter Timing diagram, setting of OCFnx, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn OCRnx - 1 OCRnx OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value OCFnx Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 16-13. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O/8) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICF n (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value 16.12 Register description 16.12.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 16-3 on page 134 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 16-3. Compare Output mode, fast PWM (1). COMnA1/COMnB1 COMnA0/COMnB0 0 0 Normal port operation, OCnA/OCnB disconnected. 0 1 WGMn3:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Waveform Generation mode bit description (1). Table 16-5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written.
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ATmega164A/PA/324A/PA/644A/PA/1284/P A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 16.12.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 16.12.7 OCR1BH and OCR1BL – Output Compare Register1 B Bit 7 6 5 4 3 (0x8B) OCR1B[15:8] (0x8A) OCR1B[7:0] 2 1 0 OCR1BH OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin.
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ATmega164A/PA/324A/PA/644A/PA/1284/P temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 113. 16.12.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See Section “11.3” on page 55) is executed when the TOV1 Flag, located in TIFR1, is set. 16.12.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 4:3 – Reserved These bits are unused and will always read as zero. • Bit 2 – OCF3B: Timer/Counter3, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output Compare Register B (OCR3B). Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag. OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17. 8-bit Timer/Counter2 with PWM and asynchronous operation 17.1 Features • • • • • • • 17.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.4 Counter unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surrounding environment. Figure 17-2. Counter Unit block diagram. TOVn (Int.Req.) DATA BUS TOSC1 count TCNTn clear clk Tn Control Logic Prescaler T/C Oscillator direction bottom TOSC2 top clkI/O Signal description (internal signals): count Increment or decrement TCNT2 by 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see ”Modes of operation” on page 148). Figure 16-10 on page 131 shows a block diagram of the Output Compare unit. Figure 17-3. Output Compare unit, block diagram. DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform generation.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2x state before the output is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of operation. See ”Register description” on page 157. 17.6.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The timing diagram for the CTC mode is shown in Table 17-5 on page 149. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 17-5. CTC mode, timing diagram. OCnx Interrupt Flag Set TCNTn OCnx (Toggle) Period (COMnx1:0 = 1) 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag.
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ATmega164A/PA/324A/PA/644A/PA/1284/P for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 17-6 on page 150.
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ATmega164A/PA/324A/PA/644A/PA/1284/P A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 17.7.
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ATmega164A/PA/324A/PA/644A/PA/1284/P In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when WGM2:0 = 7 (See Table 17-4 on page 158). The actual OC2x value will only be visible on the port pin if the data direction for the port pin is set as output.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-8. Timer/Counter Timing diagram, no prescaling. clkI/O clkTn (clkI/O /1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-9 on page 153 shows the same timing data, but with the prescaler enabled. Figure 17-9. Timer/Counter Timing diagram, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-10 on page 153 shows the setting of OCF2A in all modes except CTC mode. Figure 17-10.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 17-11 on page 154 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 17-11. Timer/Counter Timing diagram, Clear Timer on Compare Match mode, with prescaler (fclk_I/O/8). clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 OCRnx TOP BOTTOM BOTTOM + 1 TOP OCFnx 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.10 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2. PSRASY clkT2S/1024 clkT2S/256 clkT2S/128 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear clkT2S/32 TOSC1 clkT2S clkT2S/8 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.11 Register description 17.11.1 TCCR2A – Timer/Counter Control Register A Bit 7 6 5 4 3 2 1 0 COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB0) TCCR2A • Bits 7:6 – COM2A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC2A) behavior.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 17-4 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Table 17-4. Compare Output mode, phase correct PWM mode (1). COM2A1 COM2A0 0 0 Normal port operation, OC2A disconnected. 0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected. WGM22 = 1: Toggle OC2A on Compare Match. 1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare Match when down-counting.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM mode” on page 149 for more details. Table 17-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode. Compare Output mode, phase correct PWM mode (1). Table 17-7. COM2B1 COM2B0 0 0 Normal port operation, OC2B disconnected.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.11.2 TCCR2B – Timer/Counter Control Register B Bit 7 6 5 4 3 2 1 0 FOC2A FOC2B – – WGM22 CS22 CS21 CS20 Read/Write W W R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0xB1) TCCR2B • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written when operating in PWM mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-9 on page 160. Table 17-9. 17.11.3 Clock Select bit description. CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.11.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. 17.11.
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ATmega164A/PA/324A/PA/644A/PA/1284/P one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 18. SPI – Serial Peripheral Interface 18.1 Features • • • • • • • • 18.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data.
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ATmega164A/PA/324A/PA/644A/PA/1284/P When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 18-1. For more details on automatic port overrides, refer to ”Alternate Port Functions” on page 77. Table 18-1. Pin SPI pin overrides (1). Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 18.3 18.3.1 SS pin functionality Slave mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 18-2. SPI modes. SPI Mode Conditions Leading Edge Trailing Edge 0 CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 1 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 2 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 3 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) Figure 18-3. SPI transfer format with CPHA = 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 18.5 18.5.1 Register description SPCR – SPI Control Register Bit 7 6 5 4 3 2 1 0 0x2C (0x4C) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SPCR • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table: Table 18-5. 18.5.2 Relationship between SCK and the oscillator frequency.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 18.5.3 SPDR – SPI Data Register Bit 7 6 5 4 3 2 1 0 0x2E (0x4E) MSB LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X SPDR Undefined The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 19. USART 19.1 Features • • • • • • • • • • • • 19.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-1. USART block diagram (1). Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATA BUS PARITY GENERATOR TxD Receiver UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRB RxD UCSRC 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 19-2 shows a block diagram of the clock generation logic. Figure 19-2. Clock Generation Logic, block diagram.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-1. Equations for calculating baud rate register setting.
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ATmega164A/PA/324A/PA/644A/PA/1284/P duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f OSC f XCK  ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 19.4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-4. Frame formats. FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting.
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ATmega164A/PA/324A/PA/644A/PA/1284/P check that there are no unread data in the receive buffer. Note that the TXCn Flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 19.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1)(2) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRnB,TXB8 sbrc r17,0 sbi UCSRnB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDRn,r16 ret C Code Example (1)(2) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret C Code Example (1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRnA & (1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Receive: ; Wait for data to be received sbis UCSRnA, RXCn rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRnA in r17, UCSRnB in r16, UDRn ; If error, return -1 andi r18,(1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P 19.8.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data).
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ATmega164A/PA/324A/PA/644A/PA/1284/P with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 19.8.
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ATmega164A/PA/324A/PA/644A/PA/1284/P larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity). Figure 19-5. Start bit sampling.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 19-7. Stop Bit Sampling and Next Start Bit Sampling. RxD STOP 1 (A) (B) (C) Sample 1 (U2X = 0) 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample 1 (U2X = 1) 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0). D # (Data+Parity Bit) Rslow [%] Rfast [%] Maximum total error [%] Recommended max. receiver error [%] 5 93.20 106.67 +6.67/-6.8 ±3.0 6 94.12 105.79 +5.79/-5.88 ±2.5 7 94.81 105.11 +5.11/-5.19 ±2.0 8 95.36 104.58 +4.58/-4.54 ±2.0 9 95.81 104.14 +4.14/-4.19 ±1.5 10 96.17 103.78 +3.78/-3.83 ±1.5 Table 19-3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 19.11 Register description 19.11.1 UDRn – USART I/O Data Register n Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDRn (Read) TXB[7:0] UDRn (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable n Writing this bit to one enables the USART Receiver. The Receiver will override normal port operation for the RxDn pin when enabled.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 19-5. UPMn bits settings.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 19-8. Transmitted data changed (output of TxDn pin) Received data sampled (input on RxDn pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge UCPOLn 19.11.5 UCPOLn bit settings.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 19.12 Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRR settings in Table 19-9 to Table 19-12. UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-10. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud rate [bps] UBRR 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-11. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 8.0000MHz fosc = 11.0592MHz fosc = 14.7456MHz Baud rate [bps] UBRR 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 19-12. Examples of UBRRn settings for commonly used oscillator frequencies. (Continued) fosc = 16.0000MHz fosc = 18.4320MHz fosc = 20.0000MHz Baud rate [bps] UBRR 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 20. USART in SPI mode 20.1 Features • • • • • • • • 20.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 20.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in Figure 20-1. Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in Table 20-2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 20.5.1 USART MSPIM Initialization The USART in MSPIM mode has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting master mode of operation (by setting DDR_XCKn to one), setting frame format and enabling the Transmitter and the Receiver. Only the transmitter can operate independently.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Assembly Code Example (1) USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P transmitter controls the transfer clock. The data written to UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 20.6.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 20.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. 20.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 20.8 Register description The following section describes the registers used for SPI operation using the USART. 20.8.1 UDRn – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation. See “UDRn – USART I/O Data Register n” on page 193. 20.8.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn Flag. A USART Transmit Complete interrupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 5:3 – Reserved in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRnC is written. • Bit 2 – UDORDn: Data Order When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to ”Frame Formats” on page 203 for details.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21. Two-wire Serial Interface 21.1 Features • • • • • • • • • • 21.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The Power Reduction TWI bit, PRTWI bit in ”PRR0 – Power Reduction Register 0” on page 48 must be written to zero to enable the two-wire Serial Interface. 21.2.2 Electrical Interconnection As depicted in Figure 21-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface.
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ATmega164A/PA/324A/PA/644A/PA/1284/P depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 21-3. START, REPEATED START and STOP conditions. SDA SCL START 21.3.3 STOP REPEATED START START STOP Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21.3.4 Data Packet Format All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the Master generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: • An algorithm must be implemented allowing only one of the masters to complete the transmission.
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ATmega164A/PA/324A/PA/644A/PA/1284/P bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet. Figure 21-8. Arbitration between two masters.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 21-9. All registers drawn in a thick line are accessible through the AVR data bus. Figure 21-9. Overview of the TWI module.
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ATmega164A/PA/324A/PA/644A/PA/1284/P CPU Clock frequency SCL frequency = ----------------------------------------------------------TWPS 16 + 2(TWBR)  4 • TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register Note: 21.5.3 Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See two-wire Serial Bus Requirements in Table 28-16 on page 340 for value of pull-up resistor.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • After the TWI has transmitted SLA+R/W • After the TWI has transmitted an address byte • After the TWI has lost arbitration • After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a Slave • When a bus error has occurred due to an illegal START or STOP condition 21.6 Using the TWI The AVR TWI is byte-oriented and interrupt based.
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ATmega164A/PA/324A/PA/644A/PA/1284/P not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has successfully been sent. 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting In the following an assembly and C implementation of the example is given.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21.7 Transmission modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-11. Data transfer in Master Transmitter mode. VCC Device 1 Device 2 MASTER TRANSMITTER SLAVE RECEIVER Device 3 ........
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ATmega164A/PA/324A/PA/644A/PA/1284/P After a repeated START condition (state 0x10) the two-wire Serial Interface can access the same Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 21-2. Status Code (TWSR) Prescaler Bits are 0 Status codes for Master Transmitter mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-12. Formats and states in the Master Transmitter mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-13. Data transfer in Master Receiver mode. VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER Device 3 ........
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ATmega164A/PA/324A/PA/644A/PA/1284/P enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 21-3. Status Code (TWSR) Prescaler Bits are 0 Status codes for Master Receiver mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-14. Formats and states in the Master Receiver mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The upper seven bits are the address to which the two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR value TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-4. Status Code (TWSR) Prescaler Bits are 0 Status codes for Slave Receiver mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-16. Formats and states in the Slave Receiver mode. Reception of the own slave address and one or more data bytes.
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ATmega164A/PA/324A/PA/644A/PA/1284/P To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the two-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 21-5. Status Code (TWSR) Prescaler Bits are 0 0xA8 0xB0 0xB8 0xC0 0xC8 Status codes for Slave Transmitter mode.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-18. Formats and states in the Slave Transmitter mode. Reception of the own slave address and one or more data bytes S SLA R A DATA $A8 Arbitration lost as master and addressed as slave A DATA $B8 A P or S $C0 A $B0 Last data byte transmitted. Switched to not addressed slave (TWEA = '0') A All 1's P or S $C8 DATA From master to slave From slave to master 21.7.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The Master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit.
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ATmega164A/PA/324A/PA/644A/PA/1284/P bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. • Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high. 21.9.
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ATmega164A/PA/324A/PA/644A/PA/1284/P of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7:0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the two-wire Serial Bus. 21.9.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 21-22. TWI address match logic, block diagram. TWAR0 Address Match Address Bit 0 TWAMR0 Address Bit Comparator 0 Address Bit Comparator 6..1 • Bit 0 – Reserved This bit is reserved and will always read as zero.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 22. AC - Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 22-1. 22.3 22.3.1 Analog Comparator Mulitiplexed input. (Continued) ACME ADEN MUX2..
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 23. ADC - Analog-to-digital converter 23.1 Features • • • • • • • • • • • • • • • 10-bit resolution 0.5LSB integral non-linearity ±2LSB absolute accuracy 13 - 260µs conversion time Up to 15kSPS at maximum resolution Eight multiplexed single ended input channels Differential mode with selectable gain at 1×, 10×, or 200× Optional left adjustment for ADC result readout 0 - VCC ADC input voltage range 2.7 - VCC differential ADC voltage range Selectable 2.56V or 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-1. Analog-to-digital Converter block schematic. ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] ADSC ADATE TRIGGER SELECT AREF ADC[9:0] ADIF ADPS[2:0] ADEN DIFF / GAIN SELECT CHANNEL SELECTION INTERNAL REFERENCE (1.1V/2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-2. ADC auto trigger logic. ADTS[2:0] PRESCALER START ADIF CLKADC ADATE SOURCE 1 . . . . CONVERSION LOGIC EDGE DETECTOR SOURCE n ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA.
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ATmega164A/PA/324A/PA/644A/PA/1284/P in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See ”Differential Gain Channels” on page 250 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-5. ADC Timing diagram, single conversion. One Conversion Cycle Number 2 1 3 4 5 6 7 8 Next Conversion 10 9 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold MUX and REFS Update Conversion Complete MUX and REFS Update Figure 23-6. ADC Timing diagram, auto triggered conversion.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 23-1. ADC conversion time. Condition Conversion time (cycles) First conversion 14.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Auto Triggered conversions Normal conversions, differential 23.5.1 Sample & Hold (cycles from start of conversion) Differential Gain Channels When using differential gain channels, certain aspects of the conversion need to be taken into consideration.
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ATmega164A/PA/324A/PA/644A/PA/1284/P If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings.
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ATmega164A/PA/324A/PA/644A/PA/1284/P If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Signal components higher than the Nyquist frequency (fADC/2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 23-8. Analog input circuitry. IIH ADCn 1..
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ATmega164A/PA/324A/PA/644A/PA/1284/P 23.7.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. b.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 23.7.4 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5LSB). Ideal value: 0LSB Figure 23-10. Offset error.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-12. Integral non-linearity (INL). Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1LSB). Ideal value: 0LSB Figure 23-13. Differential non-linearity (DNL).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 23.8 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN  1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 23-3 on page 259 and Table 23-4 on page 260).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 23-14. Differential measurement range. Output Code 0x1FF 0x000 - V REF/GAIN 0x3FF 0 VREF/GAIN Differential Input Voltage (Volts) 0x200 Table 23-2. Correlation between input voltage and output codes. VADCn Read code Corresponding decimal value VADCm + VREF/GAIN 0x1FF 511 VADCm + 0.999VREF/GAIN 0x1FF 511 VADCm + 0.998VREF/GAIN 0x1FE 510 ... ... ... VADCm + 0.001VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 0.001VREF/GAIN 0x3FF -1 ... ...
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ATmega164A/PA/324A/PA/644A/PA/1284/P Example: ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.56V reference, left adjusted result) Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV. ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270 ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. 23.9 23.9.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 23-4. Input channel and gain selections. MUX4..
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ATmega164A/PA/324A/PA/644A/PA/1284/P 23.9.2 ADCSRA – ADC Control and Status Register A Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 (0x7A) ADCSRA • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 23-5. 23.9.3 ADC prescaler selections.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 7, 5:3 – Reserved These bits are reserved for future use in the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. For ensuring compatibility with future devices, these bits must be written zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 24. JTAG interface and on-chip debug system 24.1 Features • JTAG (IEEE std. 1149.1 Compliant) interface • Boundary-scan capabilities according to the IEEE std. 1149.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • TCK: Test Clock. JTAG operation is synchronous to TCK • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains) • TDO: Test Data Out. Serial output data from Instruction Register or Data Register The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the TAP controller is in reset.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 24-2. TAP controller state diagram. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, PauseIR, and Exit2-IR states are only used for navigating the state machine • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state.
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ATmega164A/PA/324A/PA/644A/PA/1284/P A debugger, like the Atmel AVR Studio, may however use one or more of these resources for its internal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in ”On-chip Debug Specific JTAG Instructions” on page 268. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The JTAG programming capability supports: • Flash programming and verifying • EEPROM programming and verifying • Fuse programming and verifying • Lock bit programming and verifying The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25.3 Data Registers The Data Registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain 25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 25-2. Reset register. To TDO From Other Internal and External Reset Sources From TDI D Q Internal reset ClockDR · AVR_RESET 25.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See ”Boundary-scan Chain” on page 273 for a complete description. 25.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25.4.2 IDCODE; 0x1 Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register consists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain • Shift-DR: The IDCODE scan chain is shifted by the TCK input 25.4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P The Boundary-scan logic is not included in the figures in the datasheet. Figure 25-4 shows a simple digital port pin as described in the section ”I/O-Ports” on page 72. The Boundary-scan details from Figure 25-3 replaces the dashed box in Figure 25-4 on page 275.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 25-4. General Port Pin schematic diagram. See Boundary-scan Description for Details! PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WRx IDxn DATA BUS RDx RESET SLEEP RRx SYNCHRONIZER D Q D RPx Q PINxn L Q Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: 25.5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25.6 Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order Table 25-1 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port K is scanned in the opposite bit order of the other ports.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 25-1. ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order. (Continued) Bit number Signal name 39 PD0.Data 38 PD0.Control 37 PD1.Data 36 PD1.Control 35 PD2.Data 34 PD2.Control 33 PD3.Data 32 PD3.Control 31 PD4.Data 30 PD4.Control 29 PD5.Data 28 PD5.Control 27 PD6.Data 26 PD6.Control 25 PD7.Data 24 PD7.Control 23 PC0.Data 22 PC0.Control 21 PC1.Data 20 PC1.Control 19 PC6.Data 18 PC6.Control 17 PC7.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 25-1. 25.7 ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P Boundary-scan order. (Continued) Bit number Signal name 14 PA7.Control 13 PA6.Data 12 PA6.Control 11 PA5.Data 10 PA5.Control 9 PA4.Data 8 PA4.Control 7 PA3.Data 6 PA3.Control 5 PA2.Data 4 PA2.Control 3 PA1.Data 2 PA1.Control 1 PA0.Data 0 PA0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25.8 25.8.1 Register description MCUCR – MCU Control Register The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD BODS(1) BODSE(1) PUD – – IVSEL IVCE Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Note: MCUCR 1. Only available in the Atmel ATmega164PA/324PA/644PA/1284P.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26. Boot loader support – read-while-write self-programming 26.1 Features • • • • • • • Read-while-write self-programming Flexible boot memory size High security (separate Boot Lock bits for a flexible protection) Separate fuse to select reset vector Optimized page (1) size Code efficient algorithm Efficient read-modify-write support Note: 26.2 1. A page is a section in the Flash consisting of several bytes (see Table 27-7 on page 301) used during programming.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.4 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on which address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite (NRWW) section.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 26-1. Read-While-Write vs. No Read-While-Write.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 26-2. Memory sections.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 26-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or (E)LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and (E)LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.7 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the program space is larger than 64K bytes.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 26.8.
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ATmega164A/PA/324A/PA/644A/PA/1284/P SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Table 26-5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.13 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z-pointer ;-error handling is not included ;-the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write).
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ATmega164A/PA/324A/PA/644A/PA/1284/P sbiw loophi:looplo, 1 brne Rdloop ;use subi for PAGESIZEB<=256 ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.14 Atmel ATmega164A/ATmega164PA Boot Loader Parameters In Table 26-7 through Table 26-9, the parameters used in the description of the Self-Programming are given. Table 26-7. Boot size configuration (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.15 Atmel ATmega324A/ATmega324PA Boot Loader Parameters In Table 26-10 through Table 26-12, the parameters used in the description of the Self-Programming are given. Table 26-10. Boot size configuration (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.16 Atmel ATmega644A/ATmega644PA Boot Loader parameters In Table 26-13 through Table 26-15, the parameters used in the description of the Self-Programming are given. Table 26-13. Boot size configuration (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.8.17 Atmel ATmega1284/ATmega1284P Boot Loader parameters In Table 26-16 through Table 26-18, the parameters used in the description of the Self-Programming are given. Table 26-16. Boot size configuration (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 26.9 26.9.1 Register description SPMCSR – Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Boot Loader operations.
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ATmega164A/PA/324A/PA/644A/PA/1284/P • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27. Memory programming 27.1 Program And Data Memory Lock Bits The Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 27-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1. Lock Bit byte (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-2. Lock Bit protection modes (1)(2). (Continued) Memory Lock bits BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or (E)LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-4. Fuse High byte. Fuse High byte Bit no. Description Default value OCDEN (4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN 6 Enable JTAG 0 (programmed, JTAG enabled) SPIEN (1) 5 Enable Serial Program and Data Downloading 0 (programmed, SPI prog.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. 27.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-8. Number of words in a page and number of pages in the EEPROM. Device EEPROM size Page size PCWORD No. of pages PCPAGE EEAMSB ATmega164A/ATmega164PA 512bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8 ATmega324A/ATmega324PA 1KBytes 4 bytes EEA[1:0] 256 EEA[9:2] 9 ATmega644A/ATmega644PA 2KBytes 8 bytes EEA[2:0] 256 EEA[10:2] 10 ATmega1284/ATmega1284P 4KBytes 8 bytes EEA[2:0] 512 EEA[11:3] 11 27.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-9. Pin name mapping. Signal name in programming mode Pin name I/O Function RDY/BSY PD1 O 0: Device is busy programming, 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1. XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-13. Command byte bit encoding. Command byte 27.7 27.7.1 Command executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM Parallel programming Enter Programming mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 27.7.4 Programming the Flash The Flash is organized in pages, see Table 27-7 on page 301.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “01”. This selects the address high byte. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H. Load Address Extended High byte (Address bits 23..16) 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS2, BS1 to “10”. This selects the address extended high byte. 3. Set DATA = Address extended high byte (0x00 - 0xFF). 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-3. Programming the flash waveforms (1). F DATA A B C D E 0x10 ADDR. LOW DATA LOW DATA HIGH XX B ADDR. LOW C D DATA LOW DATA HIGH E XX G H ADDR. HIGH ADDR. EXT.H I XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL Note: 27.7.5 1. “XX” is don’t care. The letters refer to the programming description above. Programming the EEPROM The EEPROM is organized in pages, see Table 27-8 on page 302.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-4. Programming the EEPROM waveforms. K DATA A G 0x11 ADDR. HIGH B ADDR. LOW C DATA E XX B ADDR. LOW C DATA E L XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 27.7.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to ”Programming the Flash” on page 305 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. H: Load Address Extended Byte (0x00- 0xFF). 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to ”Programming the Flash” on page 305 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS2, BS1 to “01”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2, BS1 to “00”. This selects low data byte.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to ”Programming the Flash” on page 305 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, and BS2, BS1 to “00”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, and BS2, BS1 to “11”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.7.15 Parallel Programming Characteristics Table 27-14. Parallel programming characteristics, VCC = 5V ±10%. Symbol Parameter Min. VPP Programming Enable Voltage 11.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-7. Parallel programming timing, including some general timing requirements. tXLWL tXHXL XTAL1 tDVXH tXLDX Data & Contol (DATA, XA0/1, BS1, BS2) tPLBX t BVWL tBVPH PAGEL tWLBX tPHPL tWLWH WR tPLWL WLRL RDY/BSY tWLRH Figure 27-8. Parallel programming timing, loading sequence with timing requirements (1).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.8 Serial downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RESET is pulled to GND. The serial programming interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 27-15, the pin mapping for serial programming is listed.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.8.2 Serial Programming Algorithm When writing serial data to the Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the rising edge of SCK. When reading data from the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P, data is clocked on the falling edge of SCK. See Figure 27-12 for timing details.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-16. Minimum wait delay before writing the next flash or EEPROM location. 27.9 Symbol Minimum wait delay tWD_FLASH 4.5ms tWD_EEPROM 3.6ms tWD_ERASE 9.0ms Serial Programming Instruction set Table 27-17 and Figure 27-11 on page 316 describes the Instruction set. Table 27-17. Serial programming instruction set (hexadecimal values).
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ATmega164A/PA/324A/PA/644A/PA/1284/P Notes: 1. 2. 3. 4. 5. Not all instructions are applicable for all parts. a = address. Bits are programmed ‘0’, unprogrammed ‘1’. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. Instructions accessing program memory use a word address. This address may be random within the page range. Note: See http://www.atmel.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.9.1 Serial Programming Characteristics For characteristics of the Serial Programming module see “SPI timing characteristics” on page 339. Figure 27-12. Serial programming waveforms. SERIAL DATA INPUT (MOSI) MSB LSB SERIAL DATA OUTPUT (MISO) MSB LSB SERIAL CLOCK INPUT (SCK) SAMPLE 27.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-13. State machine sequence for changing the instruction word. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 0 Shift-DR 1 1 Exit1-DR 0 0 Pause-DR 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.10.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.10.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.10.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-15. Programming command register.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. Set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx 2a.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 27-18. JTAG programming instruction. (Continued) Set (Continued) a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care. Instruction TDI sequence TDO sequence Notes 8e. Read Lock Bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) 8f.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 27-16. State machine sequence for changing/reading the data word. 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 Exit1-DR 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 1 0 1 Update-IR 0 1 0 27.10.
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ATmega164A/PA/324A/PA/644A/PA/1284/P ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 27-17. Flash data byte register.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 27.10.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-14 on page 311). 27.10.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 327. 1. Enter JTAG instruction PROG_COMMANDS. 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b, 3c, and 3d. PCWORD (refer to Table 27-7 on page 301) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-14 on page 311). 27.10.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28. Electrical characteristics Absolute maximum ratings* Operating temperature................................... -55C to +125C *NOTICE: Storage temperature...................................... -65°C to +150°C Voltage on any pin except RESET with respect to ground ............................... -0.5V to VCC + 0.5V Voltage on RESET with respect to ground ......-0.5V to +13.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-1. TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). (Continued) Symbol Parameter Condition VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V Notes: Min. Typ. Max. Units <10 40 mV 50 nA -50 750 500 ns 1. "Max.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.1 Atmel ATmega164A DC characteristics Table 28-2. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.4 3.5 Active 8MHz, VCC = 5V 4.8 12 Idle 1MHz, VCC = 2V 0.07 0.5 Idle 4MHz, VCC = 3V 0.25 1.5 Idle 8MHz, VCC = 5V 1.0 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.3 Atmel ATmega324A DC characteristics Table 28-4. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Max. Active 1MHz, VCC = 2V 0.3 0.55 Active 4MHz, VCC = 3V 1.5 3.5 Active 8MHz, VCC = 5V 5.2 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.35 1.5 Idle 8MHz, VCC = 5V 1.3 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.5 Atmel ATmega644A DC characteristics Table 28-6. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Max. Active 1MHz, VCC = 2V 0.38 0.5 Active 4MHz, VCC = 3V 1.8 2.7 Active 8MHz, VCC = 5V 5.6 9.0 Idle 1MHz, VCC = 2V 0.06 0.15 Idle 4MHz, VCC = 3V 0.2 0.7 Idle 8MHz, VCC = 5V 1.1 2.5 32kHz TOSC enabled, VCC = 1.8V 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.1.7 Atmel ATmega1284 DC characteristics Table 28-8. Symbol TA = -40C to 85C, VCC = 1.8V to 5.5V (unless otherwise noted). Parameter Power Supply Current (1) ICC Power-save mode (3) Power-down mode (3) Notes: Max. Active 1MHz, VCC = 2V 0.38 0.55 Active 4MHz, VCC = 3V 1.8 3.5 Active 8MHz, VCC = 5V 5.6 12 Idle 1MHz, VCC = 2V 0.06 0.5 Idle 4MHz, VCC = 3V 0.2 1.5 Idle 8MHz, VCC = 5V 1.1 5.5 32kHz TOSC enabled, VCC = 1.8V 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.2 Speed grades Maximum frequency is depending on VCC. As shown in Figure 28-1, the maximum frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 28-1. Maximum frequency vs. VCC, ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. 20MHz 10MHz Safe operating area 4MHz 1.8V 2.7V 4.5V 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.3 Clock characteristics Table 28-10. Calibration accuracy of internal RC oscillator. Frequency VCC 8.0MHz 3V Factory calibration User calibration Notes: 7.3 - 8.1MHz 1.8 - 5.5V (1) Temperature Calibration accuracy 25C ±10% -40C - 85C ±1% 1. Voltage range for Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P. 28.3.1 External clock drive waveforms Figure 28-2. External clock drive waveforms. V IH1 V IL1 28.3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.4 System and reset characteristics Table 28-12. Reset, Brown-out and Internal Voltage Reference characteristics. Symbol Parameter Condition Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling) VRST RESET Pin Threshold Voltage tRST Minimum pulse width on RESET Pin VHYST (1) Min. Typ. Max. 1.1 1.4 1.6 0.6 1.3 1.6 0.2VCC Units V 0.9VCC 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.6 SPI timing characteristics See Figure 28-3 on page 339 and Figure 28-4 on page 340 for details. Table 28-15. SPI timing parameters. Description Mode 1 SCK period Master See Table 18-5 on page 173 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 28-4. SPI interface timing requirements (Slave mode). SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) 28.7 17 MSB ... LSB X two-wire Serial Interface Characteristics Ta ble 28 -16 descr ib es th e r equirem ents for d evice s con nected to the two-wire Se r ial Bus.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-16. two-wire serial bus requirements. (Continued) Symbol Parameter tHIGH High period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT Data hold time tSU;DAT Data setup time tSU;STO Setup time for STOP condition tBUF Bus free time between a STOP and START condition Notes: Condition Min. Max. fSCL  100kHz 4.0 – fSCL > 100kHz 0.6 – fSCL  100kHz 4.7 – fSCL > 100kHz 0.6 – fSCL  100kHz 0 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.8 ADC characteristics Table 28-17. ADC characteristics, single ended channel. Symbol Typ. (1) Max. (1) Condition Resolution Single Ended Conversion 10 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 1.9 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 3.25 Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels. Symbol Parameter Resolution Absolute Accuracy (Including INL, DNL Quantization Error and Offset Error) Integral Non-linearity (INL) Differential Non-linearity (DNL) Condition Min. (1) Typ.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table 28-18. ADC characteristics, differential channels. (Continued) Symbol Parameter Gain Error Offset Error Min. (1) Gain = 1× VCC = 5V, VREF = 4V ADC clock = 200kHz 18 Gain = 10× VCC = 5V, VREF = 4V ADC clock = 200kHz 19 Gain = 200× VCC = 5V, VREF = 4V ADC clock = 200kHz 1.5 Gain = 1× VCC = 5V, VREF = 4V ADC clock = 200kHz -1 Gain = 10× VCC = 5V, VREF = 4V ADC clock = 200kHz -1 Gain = 200× VCC = 5V, VREF = 4V ADC clock = 200kHz 1 Max.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29. Typical characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1 29.1.1 Atmel ATmega164A typical characteristics Active supply current Figure 29-1. ATmega164A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-2. ATmega164A: Active supply current vs. frequency (1 - 20MHz). 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-3. Atmel ATmega164A: Active supply current vs. VCC (internal RC oscillator, 8MHz). 6 85°C 25°C -40°C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-4. Atmel ATmega164A: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-5. Atmel ATmega164A: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.1.2 Idle supply current Figure 29-6. Atmel ATmega164A: Idle supply current vs. VCC (0.1 - 1.0MHz). 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-7. Atmel ATmega164A: Idle supply current vs. VCC (1 - 20MHz). 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-8. Atmel ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-9. Atmel ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.35 -40°C 25°C 85°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-10. Atmel ATmega164A: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 0.10 25°C 85°C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-1. PRR bit Additional current consumption for the different I/O modules (absolute values).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.4 Power-down supply current Figure 29-11. Atmel ATmega164A: Power-down supply current vs. VCC (watchdog timer disabled). 1.6 85°C 1.4 1.2 ICC [µA] 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-12. Atmel ATmega164A: Power-down supply current vs. VCC (watchdog timer enabled). 10 -40°C 25°C 85°C ICC [µA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.5 Power-save supply current Figure 29-13. Atmel ATmega164A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 1.8 1.5 25°C ICC [µA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.1.6 Standby supply current Figure 29-14. Atmel ATmega164A: Standby supply current vs. VCC (watchdog timer disabled). 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.7 Pin pull-up Figure 29-15. Atmel ATmega164A: I/O pin pull-up resistor current vs. Input voltage (VCC = 1.8V). 50 45 40 IOP [µA] 35 30 25 20 15 25°C 85°C -40°C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 29-16. Atmel ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-17. Atmel ATmega164A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 25°C 20 85°C -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 29-18. Atmel ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.5 1.0 1.5 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-19. Atmel ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-20. Atmel ATmega164A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.8 Pin driver strength Figure 29-21. Atmel ATmega164A: I/O pin output voltage vs. sink current (VCC = 3V). 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 29-22. Atmel ATmega164A: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-23. Atmel ATmega164A: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 29-24. Atmel ATmega164A: I/O pin output voltage vs. source current (VCC = 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.9 Pin threshold and hysteresis Figure 29-25. Atmel ATmega164A: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-26. Atmel ATmega164A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-27. Atmel ATmega164A: I/O pin input hysteresis vs. VCC. 0.6 -40°C 25°C 85°C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-28. Atmel ATmega164A: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-29. Atmel ATmega164A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-30. Atmel ATmega164A: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.10 BOD threshold Figure 29-31. Atmel ATmega164A: BOD threshold vs. temperature (VBOT = 4.3V). 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-32. Atmel ATmega164A: BOD threshold vs. temperature (VBOT = 2.7V). 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-33. Atmel ATmega164A: BOD threshold vs. temperature (VBOT = 1.8V). 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-34. Atmel ATmega164A: Calibrated bandgap voltage vs. VCC. 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25°C 85°C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-35. Atmel ATmega164A: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.1.11 Internal oscillator speed Figure 29-36. Atmel ATmega164A: Watchdog oscillator frequency vs. temperature. 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-37. Atmel ATmega164A: Watchdog oscillator frequency vs. VCC. 135 132 FRC [kHz] -40°C 129 25°C 126 123 85°C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-38. Atmel ATmega164A: Calibrated 8MHz RC oscillator vs. VCC. 8.4 85°C 8.2 FRC [MHz] 8.0 25°C 7.8 -40°C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-39. Atmel ATmega164A: Calibrated 8MHz RC oscillator vs. temperature. 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-40. Atmel ATmega164A: Calibrated 8MHz RC oscillator vs. OSCCAL value.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.12 Current consumption of peripheral units Figure 29-41. Atmel ATmega164A: ADC current vs. VCC (AREF = AVCC). 320 -40°C 85°C 25°C 280 240 ICC [µA] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-42. Atmel ATmega164A: Analog comparator current vs. VCC. 100 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-43. Atmel ATmega164A: AREF external reference current vs. VCC. 200 25°C 85°C -40°C ICC [µA] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-44. Atmel ATmega164A: Brownout detector current vs. VCC. 27 85°C 25°C -40°C 24 21 ICC [µA] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-45. Atmel ATmega164A: Programming current vs. VCC. 12 -40°C 25°C 85°C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-46. Atmel ATmega164A: Watchdog timer current vs. VCC. 9 -40°C 8 25°C 85°C 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.1.13 Current consumption in reset and reset pulsewidth Figure 29-47. Atmel ATmega164A: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 29-48. Atmel ATmega164A: Reset supply current vs. frequency (1 - 20MHz). 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-49. Atmel ATmega164A: Minimum reset pulsewidth vs. VCC. 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2 29.2.1 Atmel ATmega164PA typical characteristics Active supply current Figure 29-50. Atmel ATmega164PA: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 1.0 5.0V ICC [mA] 0.8 4.5V 4.0V 0.6 3.3V 0.4 2.7V 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-51. Atmel ATmega164PA: Active supply current vs. frequency (1 - 20MHz). 12 5.5V 10 5.0V 4.5V ICC [mA] 8 4.0V 6 4 3.3V 2.7V 2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-52. Atmel ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 8MHz). 6 85°C 25°C -40°C 5 ICC [mA] 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-53. Atmel ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-54. Atmel ATmega164PA: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.2.2 Idle supply current Figure 29-55. Atmel ATmega164PA: Idle supply current vs. VCC (0.1 - 1.0MHz). 0.20 5.5V 5.0V 4.5V 0.15 ICC [mA] 4.0V 3.3V 0.10 2.7V 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-56. Atmel ATmega164PA: Idle supply current vs. VCC (1 - 20MHz). 3.0 5.5V 2.5 5.0V ICC [mA] 2.0 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-57. Atmel ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.2 85°C 25°C -40°C 1.0 ICC [mA] 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-58. Atmel ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.35 -40°C 25°C 85°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-59. Atmel ATmega164PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 0.10 25°C 85°C ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-3. PRR bit Additional current consumption for the different I/O modules (absolute values).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.4 Power-down supply current Figure 29-60. Atmel ATmega164PA: Power-down supply current vs. VCC (watchdog timer disabled). 1.6 85°C 1.4 1.2 ICC [µA] 1.0 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-61. Atmel ATmega164PA: Power-down supply current vs. VCC (watchdog timer enabled). 10 -40°C 25°C 85°C ICC [µA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.5 Power-save supply current Figure 29-62. Atmel ATmega164PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 1.8 1.5 25°C ICC [µA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.2.6 Standby supply current Figure 29-63. Atmel ATmega164PA: Standby supply current vs. VCC (watchdog timer disabled). 0.20 6MHz_xtal 6MHz_res 0.18 0.16 ICC [mA] 0.14 4MHz_res 4MHz_xtal 0.12 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.7 Pin pull-up Figure 29-64. Atmel ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 IOP [µA] 35 30 25 20 15 25°C 85°C -40°C 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 29-65. Atmel ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-66. Atmel ATmega164PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 25°C 20 85°C -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 29-67. Atmel ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.5 1.0 1.5 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-68. Atmel ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-69. Atmel ATmega164PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.8 Pin driver strength Figure 29-70. Atmel ATmega164PA: I/O pin output voltage vs. sink current (VCC = 3V). 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 0 4 8 12 16 20 IOL [mA] Figure 29-71. Atmel ATmega164PA: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-72. Atmel ATmega164PA: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 4 8 12 16 20 IOH [mA] Figure 29-73. Atmel ATmega164PA: I/O pin output voltage vs. source current (VCC = 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.9 Pin threshold and hysteresis Figure 29-74. Atmel ATmega164PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-75. Atmel ATmega164PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-76. Atmel ATmega164PA: I/O pin input hysteresis vs. VCC. 0.6 -40°C 25°C 85°C Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-77. Atmel ATmega164PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-78. Atmel ATmega164PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-79. Atmel ATmega164PA: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.10 BOD threshold Figure 29-80. Atmel ATmega164PA: BOD threshold vs. temperature (VBOT = 4.3V). 4.34 Rising Vcc 4.32 Threshold [V] 4.30 4.28 4.26 Falling Vcc 4.24 4.22 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-81. Atmel ATmega164PA: BOD threshold vs. temperature (VBOT = 2.7V). 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-82. Atmel ATmega164PA: BOD threshold vs. temperature (VBOT = 1.8V). 1.850 Rising Vcc 1.845 1.840 Threshold [V] 1.835 1.830 1.825 1.820 1.815 Falling Vcc 1.810 1.805 1.80 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-83. Atmel ATmega164PA: Calibrated bandgap voltage vs. VCC. 1.109 1.107 Bandgap voltage [V] 1.105 1.103 25°C 85°C 1.101 1.099 1.097 1.095 1.093 1.091 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-84. Atmel ATmega164PA: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.2.11 Internal oscillator speed Figure 29-85. Atmel ATmega164PA: Watchdog oscillator frequency vs. temperature. 134 132 FRC [kHz] 130 128 126 2.1V 2.7V 3.3V 4.0V 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-86. Atmel ATmega164PA: Watchdog oscillator frequency vs. VCC. 135 132 FRC [kHz] -40°C 129 25°C 126 123 85°C 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-87. Atmel ATmega164PA: Calibrated 8MHz RC oscillator vs. VCC. 8.4 85°C 8.2 FRC [MHz] 8.0 25°C 7.8 -40°C 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-88. Atmel ATmega164PA: Calibrated 8MHz RC oscillator vs. temperature. 8.3 5.0V 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-89. Atmel ATmega164PA: Calibrated 8MHz RC oscillator vs. OSCCAL value.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.12 Current consumption of peripheral units Figure 29-90. Atmel ATmega164PA: ADC current vs. VCC (AREF = AVCC). 320 -40°C 85°C 25°C 280 240 ICC [µA] 200 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-91. Atmel ATmega164PA: Analog comparator current vs. VCC. 100 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-92. Atmel ATmega164PA: AREF external reference current vs. VCC. 200 25°C 85°C -40°C ICC [µA] 160 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-93. Atmel ATmega164PA: Brownout detector current vs. VCC. 27 85°C 25°C -40°C 24 21 ICC [µA] 18 15 12 9 6 3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-94. Atmel ATmega164PA: Programming current vs. VCC. 12 -40°C 25°C 85°C 10 ICC [mA] 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-95. Atmel ATmega164PA: Watchdog timer current vs. VCC. 9 -40°C 8 25°C 85°C 7 ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.2.13 Current consumption in reset and reset pulsewidth Figure 29-96. Atmel ATmega164PA: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 0.08 5.0V ICC [mA] 4.5V 0.06 4.0V 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.2 0.4 0.6 0.8 1.0 Frequency [MHz] Figure 29-97. Atmel ATmega164PA: Reset supply current vs. frequency (1 - 20MHz). 1.8 5.5V 1.5 5.0V 4.5V ICC [mA] 1.2 0.9 4.0V 0.6 3.3V 0.3 2.7V 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-98. Atmel ATmega164PA: Minimum reset pulsewidth vs. VCC. 1600 1400 Pulsewidth [ns] 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3 29.3.1 Atmel ATmega324A typical characteristics Active supply current Figure 29-99. Atmel ATmega324A: Active supply current vs. low frequency (0.1 - 1.0MHz). ICC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-100.Atmel ATmega324A: Active supply current vs. frequency (1 - 20MHz). ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-101.Atmel ATmega324A: Active supply current vs. VCC (internal RC oscillator, 8MHz). 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-102.Atmel ATmega324A: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.6 85°C 25°C -40°C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-103.Atmel ATmega324A: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.3.2 Idle supply current Figure 29-104.Atmel ATmega324A: Idle supply current vs. VCC (0.1 - 1.0MHz). 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-105.Atmel ATmega324A: Idle supply current vs. VCC (1 - 20MHz). 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-106.Atmel ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-107.Atmel ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 85°C 25°C -40°C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-108.Atmel ATmega324A: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-5. PRR bit Additional current consumption for the different I/O modules (absolute values).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.4 Power-down supply current Figure 29-109.Atmel ATmega324A: Power-down supply current vs. VCC (watchdog timer disabled). 1.2 85°C 1.0 ICC [µA] 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-110.Atmel ATmega324A: Power-down supply current vs. VCC (watchdog timer enabled). 10 -40°C 85°C 25°C 8 ICC [µA] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.5 Power-save supply current Figure 29-111.Atmel ATmega324A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 2.50 85°C 2.00 ICC [µA] 1.50 25°C -40°C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.3.6 Standby supply current Figure 29-112.Atmel ATmega324A: Standby supply current vs. VCC (watchdog timer disabled). 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.7 Pin pull-up Figure 29-113.Atmel ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 40 IOP [µA] 30 20 25°C -40°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 29-114.Atmel ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 25°C 20 85°C 10 -40°C 0 0 0.5 1.0 1.5 2.0 2.5 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-115.Atmel ATmega324A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 25°C 40 85°C 20 -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 29-116.Atmel ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 25°C 5 -40°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-117.Atmel ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-118.Atmel ATmega324A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.8 Pin driver strength Figure 29-119.Atmel ATmega324A: I/O pin output voltage vs. sink current (VCC = 3V). 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 29-120.Atmel ATmega324A: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-121.Atmel ATmega324A: I/O pin output voltage vs. source current (VCC = 3V). 3.0 2.5 -40°C 25°C 85°C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 29-122.Atmel ATmega324A: I/O pin output voltage vs. source current (VCC = 5V). 4.9 4.8 VOH [V] 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.9 Pin threshold and hysteresis Figure 29-123.Atmel ATmega324A: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 85°C 3.0 -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-124.Atmel ATmega324A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-125.Atmel ATmega324A: I/O pin input hysteresis vs. VCC. 0.6 85°C 25°C 0.5 Input hysteresis [mV] -40°C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-126.Atmel ATmega324A: Reset, pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-127.Atmel ATmega324A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). -40°C 25°C 2.5 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-128.Atmel ATmega324A: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.10 BOD threshold Figure 29-129.Atmel ATmega324A: BOD threshold vs. temperature (VBOT = 4.3V). 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-130.Atmel ATmega324A: BOD threshold vs. temperature (VBOT = 2.7V). 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-131.Atmel ATmega324A: BOD threshold vs. temperature (VBOT = 1.8V). 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-132.Atmel ATmega324A: Calibrated bandgap voltage vs. VCC. 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85°C 25°C 1.090 1.088 1.086 1.084 1.082 1.080 -40°C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-133.Atmel ATmega324A: Bandgap voltage vs. temperature. 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.3.11 Internal oscillator speed Figure 29-134.Atmel ATmega324A: Watchdog oscillator frequency vs. temperature. 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-135.Atmel ATmega324A: Watchdog oscillator frequency vs. VCC. 123 -40°C FRC [kHz] 120 25°C 117 114 85°C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-136.Atmel ATmega324A: Calibrated 8MHz RC oscillator vs. VCC. 8.6 85°C 8.2 FRC [MHz] 25°C 7.8 -40°C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-137.Atmel ATmega324A: Calibrated 8MHz RC oscillator vs. temperature. 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-138.Atmel ATmega324A: Calibrated 8MHz RC oscillator vs. OSCCAL value.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.12 Current consumption of peripheral units Figure 29-139.Atmel ATmega324A: ADC current vs. VCC (AREF = AVCC). 300 25°C 85°C -40°C 250 ICC [µA] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-140.Atmel ATmega324A: Analog comparator current vs. VCC. 90 -40°C 80 25°C 70 85°C ICC [µA] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-141.Atmel ATmega324A: AREF external reference current vs. VCC. 25°C 85°C -40°C 200 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-142.Atmel ATmega324A: Brownout detector current vs. VCC. 25 85°C 25°C -40°C 20 ICC [µA] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-143.Atmel ATmega324A: Programming current vs. VCC. 14 25°C -40°C 85°C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-144.Atmel ATmega324A: Watchdog timer current vs. VCC. 9 -40°C 25°C 85°C ICC [µA] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.3.13 Current consumption in reset and reset pulsewidth Figure 29-145.Atmel ATmega324A: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.14 5.5V 0.12 5.0V 0.10 ICC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-146.Atmel ATmega324A: Reset supply current vs. frequency (1 - 20MHz). 2.5 5.5V 2.0 5.0V ICC [mA] 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-147.Atmel ATmega324A: Minimum reset pulsewidth vs. VCC. 1800 Pulsewidth [ns] 1500 1200 900 600 85°C 25°C -40°C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4 29.4.1 Atmel ATmega324PA typical characteristics Active supply current Figure 29-148.Atmel ATmega324PA: Active supply current vs. low frequency (0.1 - 1.0MHz). ICC [mA] 1.2 5.5V 1.0 5.0V 0.8 4.5V 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-149.Atmel ATmega324PA: Active supply current vs. frequency (1 - 20MHz). ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-150.Atmel ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 8MHz). 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-151.Atmel ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.6 85°C 25°C -40°C ICC [mA] 1.2 0.8 0.4 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-152.Atmel ATmega324PA: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.25 -40°C 25°C 85°C ICC [mA] 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.4.2 Idle supply current Figure 29-153.Atmel ATmega324PA: Idle supply current vs. VCC (0.1 - 1.0MHz). 5.5V 0.25 5.0V 0.20 4.5V ICC [mA] 4.0V 0.15 3.3V 2.7V 0.10 1.8V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-154.Atmel ATmega324PA: Idle supply current vs. VCC (1 - 20MHz). 4 5.5V 5.0V 3 ICC [mA] 4.5V 2 4.0V 3.3V 1 2.7V 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-155.Atmel ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-156.Atmel ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 85°C 25°C -40°C 0.6 0.5 ICC [mA] 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-157.Atmel ATmega324PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-7. PRR bit Additional current consumption for the different I/O modules (absolute values).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.4 Power-down Supply Current Figure 29-158.Atmel ATmega324PA: Power-down supply current vs. VCC (watchdog timer disabled). 1.2 85°C 1.0 ICC [µA] 0.8 0.6 0.4 25°C -40°C 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-159.Atmel ATmega324PA: Power-down supply current vs. VCC (watchdog timer enabled). 10 -40°C 85°C 25°C 8 ICC [µA] 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.5 Power-save supply current Figure 29-160.Atmel ATmega324PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). WATCHDOG TIMER DISABLED and 32 kHz CRYSTAL OSCILLATOR RUNNING 2.50 85°C 2.00 ICC [µA] 1.50 25°C -40°C 1.00 0.50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.4.6 Standby supply current Figure 29-161.Atmel ATmega324PA: Standby supply current vs. VCC (watchdog timer disabled). 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.7 Pin pull-up Figure 29-162.Atmel ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 40 IOP [µA] 30 20 25°C -40°C 85°C 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VOP [V] Figure 29-163.Atmel ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 25°C 20 85°C 10 -40°C 0 0 0.5 1.0 1.5 2.0 2.5 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-164.Atmel ATmega324PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 25°C 40 85°C 20 -40°C 0 0 1 2 3 4 5 6 VOP [V] Figure 29-165.Atmel ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 25°C 5 -40°C 85°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-166.Atmel ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-167.Atmel ATmega324PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.8 Pin driver strength Figure 29-168.Atmel ATmega324PA: I/O pin output voltage vs. sink current (VCC = 3V). 1.0 85°C 0.8 25°C VOL [V] 0.6 -40°C 0.4 0.2 0 5 8 11 14 17 20 IOL [mA] Figure 29-169.Atmel ATmega324PA: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-170.Atmel ATmega324PA: I/O pin output voltage vs. source current (VCC = 3V). 3.0 2.5 -40°C 25°C 85°C VOH [V] 2.0 1.5 1.0 0.5 0 5 8 11 14 17 20 IOH [mA] Figure 29-171.Atmel ATmega324PA: I/O pin output voltage vs. source current (VCC = 5V). 4.9 4.8 VOH [V] 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.9 Pin threshold and hysteresis Figure 29-172.Atmel ATmega324PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 85°C 3.0 -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-173.Atmel ATmega324PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-174.Atmel ATmega324PA: I/O pin input hysteresis vs. VCC. 0.6 85°C 25°C 0.5 Input hysteresis [mV] -40°C 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-175.Atmel ATmega324PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). , -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-176.Atmel ATmega324PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). -40°C 25°C 2.5 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-177.Atmel ATmega324PA: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.10 BOD threshold Figure 29-178.Atmel ATmega324PA: BOD threshold vs. temperature (VBOT = 4.3V). 4.40 Rising Vcc 4.38 Threshold [V] 4.36 4.34 4.32 Falling Vcc 4.30 4.28 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-179.Atmel ATmega324PA: BOD threshold vs. temperature (VBOT = 2.7V). 2.80 Rising Vcc 2.78 Threshold [V] 2.76 2.74 Falling Vcc 2.72 2.70 2.68 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-180.Atmel ATmega324PA: BOD threshold vs. temperature (VBOT = 1.8V). 1.86 Rising Vcc Threshold [V] 1.84 1.82 Falling Vcc 1.80 1.78 1.76 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-181.Atmel ATmega324PA: Calibrated bandgap voltage vs. VCC. 1.098 1.096 Bandgap voltage [V] 1.094 1.092 85°C 25°C 1.090 1.088 1.086 1.084 1.082 1.080 -40°C 1.078 1.076 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-182.Atmel ATmega324PA: Bandgap voltage vs. temperature. 1.097 1.8V 3.6V 2.7V 4.5V 1.095 Bandgap voltage [V] 1.093 1.091 5.5V 1.089 1.087 1.085 1.083 1.081 1.079 1.077 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.4.11 Internal oscillator speed Figure 29-183.Atmel ATmega324PA: Watchdog oscillator frequency vs. temperature. 122 FRC [kHz] 119 116 2.1V 2.7V 3.3V 4.0V 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-184.Atmel ATmega324PA: Watchdog oscillator frequency vs. VCC. 123 -40°C FRC [kHz] 120 25°C 117 114 85°C 111 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-185.Atmel ATmega324PA: Calibrated 8MHz RC oscillator vs. VCC. 8.6 85°C 8.2 FRC [MHz] 25°C 7.8 -40°C 7.4 7.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-186.Atmel ATmega324PA: Calibrated 8MHz RC oscillator vs. temperature. 8.6 5.0V 3.0V FRC [MHz] 8.3 8.0 7.7 7.4 -40 -20 0 20 40 60 80 100 Temperature [°C] Figure 29-187.Atmel ATmega324PA: Calibrated 8MHz RC oscillator vs. OSCCAL value.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.12 Current consumption of peripheral units Figure 29-188.Atmel ATmega324PA: ADC current vs. VCC (AREF = AVCC). 300 25°C 85°C -40°C 250 ICC [µA] 200 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-189.Atmel ATmega324PA: Analog comparator current vs. VCC. 90 -40°C 80 25°C 70 85°C ICC [µA] 60 50 40 30 20 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-190.Atmel ATmega324PA: AREF external reference current vs. VCC. 25°C 85°C -40°C 200 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-191.Atmel ATmega324PA: Brownout detector current vs. VCC. 25 85°C 25°C -40°C 20 ICC [µA] 15 10 5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-192.Atmel ATmega324PA: Programming current vs. VCC. 14 25°C -40°C 85°C 12 ICC [mA] 10 8 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-193.Atmel ATmega324PA: Watchdog timer current vs. VCC. 9 -40°C 25°C 85°C ICC [µA] 7 5 3 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.4.13 Current consumption in reset and reset pulsewidth Figure 29-194.Atmel ATmega324PA: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.14 5.5V 0.12 5.0V 0.10 ICC [mA] 4.5V 0.08 4.0V 0.06 3.3V 2.7V 0.04 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-195.Atmel ATmega324PA: Reset supply current vs. frequency (1 - 20MHz). 2.5 5.5V 2.0 5.0V ICC [mA] 4.5V 1.5 4.0V 1.0 3.3V 0.5 2.7V 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-196.Atmel ATmega324PA: Minimum reset pulsewidth vs. VCC. 1800 Pulsewidth [ns] 1500 1200 900 600 85°C 25°C -40°C 300 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5 29.5.1 Atmel ATmega644A typical characteristics Active supply current Figure 29-197.Atmel ATmega644A: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-198.Atmel ATmega644A: Active supply current vs. frequency (1 - 20MHz). ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-199.Atmel ATmega644A: Active supply current vs. VCC (internal RC oscillator, 8MHz). 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-200.Atmel ATmega644A: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-201.Atmel ATmega644A: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.22 -40°C 25°C 85°C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.5.2 Idle supply current Figure 29-202.Atmel ATmega644A: Idle supply current vs. VCC (0.1 - 1.0MHz). 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-203.Atmel ATmega644A: Idle supply current vs. VCC (1 - 20MHz). 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-204.Atmel ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-205.Atmel ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.35 85°C 25°C -40°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-206.Atmel ATmega644A: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 455
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-9. PRR bit Additional Current Consumption for the different I/O modules (absolute values).
PAGE 456
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.4 Power-down supply current Figure 29-207.Atmel ATmega644A: Power-down supply current vs. VCC (watchdog timer disabled). 2.5 85°C 2.0 ICC [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-208.Atmel ATmega644A: Power-down supply current vs. VCC (watchdog timer enabled). 9 85°C 8 -40°C 25°C ICC [µA] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 457
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.5 Power-save supply current Figure 29-209.Atmel ATmega644A: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 2.5 85°C 2.0 Icc [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.5.6 Standby supply current Figure 29-210.Atmel ATmega644A: Standby supply current vs. VCC (watchdog timer disabled). 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.
PAGE 458
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.7 Pin pull-up Figure 29-211.Atmel ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 25°C 85°C -40°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 29-212.Atmel ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
PAGE 459
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-213.Atmel ATmega644A: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 25°C 85°C -40°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 29-214.Atmel ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). g p g ( ) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.
PAGE 460
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-215.Atmel ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-216.Atmel ATmega644A: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
PAGE 461
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.8 Pin driver strength Figure 29-217.Atmel ATmega644A: I/O pin output voltage vs. sink current (VCC = 3V). 0.9 85°C 0.8 0.7 25°C 0.6 VOL [V] -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-218.Atmel ATmega644A: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
PAGE 462
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-219.Atmel ATmega644A: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 29-220.Atmel ATmega644A: I/O pin output voltage vs. source current (VCC = 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
PAGE 463
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.9 Pin threshold and hysteresis Figure 29-221.Atmel ATmega644A: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-222.Atmel ATmega644A: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 464
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-223.Atmel ATmega644A: I/O pin input hysteresis vs. VCC. 0.60 25°C 85°C -40°C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-224.Atmel ATmega644A: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 465
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-225.Atmel ATmega644A: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-226.Atmel ATmega644A: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 466
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.10 BOD threshold Figure 29-227.Atmel ATmega644A: BOD threshold vs. temperature (VBOT = 4.3V). 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-228.Atmel ATmega644A: BOD threshold vs. temperature (VBOT = 2.7V). 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 467
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-229.Atmel ATmega644A: BOD threshold vs. temperature (VBOT = 1.8V). 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 29-230.Atmel ATmega644A: Calibrated bandgap voltage vs. VCC. 1.086 1.084 Bandgap voltage [V] 1.082 85°C 25°C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 468
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-231.Atmel ATmega644A: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.5.11 Internal oscillator speed Figure 29-232.Atmel ATmega644A: Watchdog oscillator frequency vs. temperature. 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.
PAGE 469
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-233.Atmel ATmega644A: Watchdog oscillator frequency vs. VCC. 119 118 117 -40°C 116 FRC [kHz] 115 25°C 114 113 112 111 110 85°C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-234.Atmel ATmega644A: Calibrated 8MHz RC oscillator vs. VCC. 8.4 85°C 8.2 25°C FRC [MHz] 8.0 -40°C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 470
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-235.Atmel ATmega644A: Calibrated 8MHz RC oscillator vs. temperature. 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [°C] Figure 29-236.Atmel ATmega644A: Calibrated 8MHz RC oscillator vs. OSCCAL value.
PAGE 471
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.12 Current consumption of peripheral units Figure 29-237.Atmel ATmega644A: ADC current vs. VCC (AREF = AVCC). 250 25°C 85°C -40°C 200 ICC [µA] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 29-238.Atmel ATmega644A: Analog comparator current vs. VCC. 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 472
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-239.Atmel ATmega644A: AREF external reference current vs. VCC. 200 25°C 85°C -40°C 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-240.Atmel ATmega644A: Brownout detector current vs. VCC. 24 85°C 22 25°C -40°C ICC [µA] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 473
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-241.Atmel ATmega644A: Programming current vs. VCC. -40°C 16 14 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-242.Atmel ATmega644A: Watchdog timer current vs. VCC. 9 8 -40°C 7 25°C 85°C ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 474
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.5.13 Current consumption in reset and reset pulsewidth Figure 29-243.Atmel ATmega644A: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-244.Atmel ATmega644A: Reset supply current vs. frequency (1 - 20MHz). 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.
PAGE 475
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-245.Atmel ATmega644A: Minimum reset pulsewidth vs. VCC. 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85°C 25°C -40°C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 476
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6 29.6.1 ATmega644PA typical characteristics Active supply current Figure 29-246.Atmel ATmega644PA: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.2 5.5V 1.0 5.0V 4.5V ICC [mA] 0.8 4.0V 0.6 3.3V 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-247.Atmel ATmega644PA: Active supply current vs. frequency (1 - 20MHz). ICC [mA] 14 5.5V 12 5.0V 10 4.5V 8 4.0V 6 3.3V 4 2.7V 2 1.
PAGE 477
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-248.Atmel ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 8MHz). 7 85°C 25°C -40°C 6 ICC [mA] 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-249.Atmel ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 478
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-250.Atmel ATmega644PA: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.22 -40°C 25°C 85°C 0.20 0.18 ICC [mA] 0.16 0.14 0.12 0.10 0.08 0.06 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.6.2 Idle supply current Figure 29-251.Atmel ATmega644PA: Idle supply current vs. VCC (0.1 - 1.0MHz). 0.24 5.5V 0.20 5.0V 4.5V 4.0V ICC [mA] 0.16 3.3V 2.7V 0.12 0.08 1.8V 0.04 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 479
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-252.Atmel ATmega644PA: Idle supply current vs. VCC (1 - 20MHz). 3.0 5.5V 5.0V 2.5 4.5V ICC [mA] 2.0 4.0V 1.5 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-253.Atmel ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.4 85°C 25°C -40°C 1.2 ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 480
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-254.Atmel ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.35 85°C 25°C -40°C 0.30 ICC [mA] 0.25 0.20 0.15 0.10 0.05 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-255.Atmel ATmega644PA: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 25°C 85°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 481
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-11. Additional current consumption for the different I/O modules (absolute values).
PAGE 482
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.4 Power-down supply current Figure 29-256.Atmel ATmega644PA: Power-down supply current vs. VCC (watchdog timer disabled). 2.5 85°C 2.0 ICC [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-257.Atmel ATmega644PA: Power-down supply current vs. VCC (watchdog timer enabled). 9 85°C 8 -40°C 25°C ICC [µA] 7 6 5 4 3 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 483
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.5 Power-save supply current Figure 29-258.Atmel ATmega644PA: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 2.5 85°C 2.0 Icc [µA] 1.5 1.0 0.5 25°C -40°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.6.6 Standby supply current Figure 29-259.Atmel ATmega644PA: Standby supply current vs. VCC (watchdog timer disabled). 0.16 6MHz_res 6MHz_xtal 0.14 4MHz_res 0.12 4MHz_xtal ICC [mA] 0.10 0.
PAGE 484
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.7 Pin pull-up Figure 29-260.Atmel ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 50 45 40 35 IOP [µA] 30 25 20 15 10 25°C 85°C -40°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VOP [V] Figure 29-261.Atmel ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 25°C 85°C -40°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
PAGE 485
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-262.Atmel ATmega644PA: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 25°C 85°C -40°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 29-263.Atmel ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). g p g ( ) 35 30 IRESET [µA] 25 20 15 10 25°C -40°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.
PAGE 486
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-264.Atmel ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-265.Atmel ATmega644PA: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V).
PAGE 487
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.8 Pin driver strength Figure 29-266.Atmel ATmega644PA: I/O pin output voltage vs. sink current (VCC = 3V). 0.9 85°C 0.8 0.7 25°C 0.6 VOL [V] -40°C 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-267.Atmel ATmega644PA: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.
PAGE 488
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-268.Atmel ATmega644PA: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] Figure 29-269.Atmel ATmega644PA: I/O pin output voltage vs. source current (VCC = 5V). 5.1 5.0 4.9 VOH [V] 4.8 4.7 4.6 -40°C 4.5 25°C 4.4 85°C 4.
PAGE 489
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.9 Pin threshold and hysteresis Figure 29-270.Atmel ATmega644PA: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C -40°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-271.Atmel ATmega644PA: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 490
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-272.Atmel ATmega644PA: I/O pin input hysteresis vs. VCC. 0.60 25°C 85°C -40°C 0.55 Input Hysteresis [mV] 0.50 0.45 0.40 0.35 0.30 0.25 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-273.Atmel ATmega644PA: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 2.5 -40°C 25°C 85°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 491
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-274.Atmel ATmega644PA: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C 25°C -40°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-275.Atmel ATmega644PA: Reset pin input hysteresis vs. VCC. 0.7 Input hysteresis [mV] 0.6 0.5 0.4 0.3 0.2 -40°C 25°C 85°C 0.1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 492
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.10 BOD threshold Figure 29-276.Atmel ATmega644PA: BOD threshold vs. temperature (VBOT = 4.3V). 4.35 Rising Vcc Threshold [V] 4.32 4.29 Falling Vcc 4.26 4.23 4.20 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-277.Atmel ATmega644PA: BOD threshold vs. temperature (VBOT = 2.7V). 2.77 Rising Vcc 2.75 Threshold [V] 2.73 2.71 Falling Vcc 2.69 2.67 2.
PAGE 493
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-278.Atmel ATmega644PA: BOD threshold vs. temperature (VBOT = 1.8V). 1.84 1.83 Rising Vcc Threshold [V] 1.82 1.81 1.80 Falling Vcc 1.79 1.78 1.77 1.76 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature [°C] Figure 29-279.Atmel ATmega644PA: Calibrated bandgap voltage vs. VCC. 1.086 1.084 Bandgap voltage [V] 1.082 85°C 25°C 1.080 1.078 1.076 1.074 1.072 1.070 1.068 1.066 1.5 -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 494
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-280.Atmel ATmega324PA: Bandgap voltage vs. temperature. 1.087 1.8V 3.6V 2.7V 4.5V 1.085 Bandgap voltage [V] 1.083 1.081 5.5V 1.079 1.077 1.075 1.073 1.071 1.069 1.067 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] 29.6.11 Internal oscillator speed Figure 29-281.Atmel ATmega644PA: Watchdog oscillator frequency vs. temperature. 119 118 117 116 FRC [kHz] 115 114 113 2.1V 112 2.7V 3.3V 4.0V 5.
PAGE 495
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-282.Atmel ATmega644PA: Watchdog oscillator orequency vs. VCC. 119 118 117 -40°C 116 FRC [kHz] 115 25°C 114 113 112 111 110 85°C 109 108 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-283.Atmel ATmega644PA: Calibrated 8MHz RC oscillator vs. VCC. 8.4 85°C 8.2 25°C FRC [MHz] 8.0 -40°C 7.8 7.6 7.4 7.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 496
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-284.Atmel ATmega644PA: Calibrated 8MHz RC oscillator vs. temperature. 8.4 5.0V 8.3 3.0V 8.2 FRC [MHz] 8.1 8.0 7.9 7.8 7.7 7.6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature [°C] Figure 29-285.Atmel ATmega644PA: Calibrated 8MHz RC oscillator vs. OSCCAL value.
PAGE 497
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.12 Current consumption of peripheral units Figure 29-286.Atmel ATmega644PA: ADC current vs. VCC (AREF = AVCC). 250 25°C 85°C -40°C 200 ICC [µA] 150 100 50 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VCC [V] Figure 29-287.Atmel ATmega644PA: Analog comparator current vs. VCC. 90 -40°C 80 25°C 85°C ICC [µA] 70 60 50 40 30 20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 498
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-288.Atmel ATmega644PA: AREF external reference current vs. VCC. 200 25°C 85°C -40°C 160 ICC [µA] 120 80 40 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-289.Atmel ATmega644PA: Brownout detector current vs. VCC. 24 85°C 22 25°C -40°C ICC [µA] 20 18 16 14 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 499
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-290.Atmel ATmega644PA: Programming current vs. VCC. -40°C 16 14 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-291.Atmel ATmega644PA: Watchdog timer current vs. VCC. 9 8 -40°C 7 25°C 85°C ICC [µA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 500
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.6.13 Current consumption in reset and reset pulsewidth Figure 29-292.Atmel ATmega644PA: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-293.Atmel ATmega644PA: Reset supply current vs. frequency (1 - 20MHz). 2.00 5.5V 1.75 5.0V 1.50 4.5V ICC [mA] 1.25 1.00 4.0V 0.75 3.3V 0.50 2.7V 0.25 1.
PAGE 501
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-294.Atmel ATmega644PA: Minimum reset pulsewidth vs. VCC. 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 85°C 25°C -40°C 400 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 502
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7 29.7.1 ATmega1284 typical characteristics Active supply current ICC [mA] Figure 29-295.Atmel ATmega1284: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-296.Atmel ATmega1284: Active supply current vs. frequency (1 - 20MHz). 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.0V 10 8 3.3V 6 2.
PAGE 503
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-297.Atmel ATmega1284: Active supply current vs. VCC (internal RC oscillator, 8MHz). 9 85°C 25°C -40°C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-298.Atmel ATmega1284: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 504
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-299.Atmel ATmega1284: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.28 -40°C 25°C 85°C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.7.2 Idle supply current Figure 29-300.Atmel ATmega1284: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 505
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-301.Atmel ATmega1284: Idle supply current vs. frequency (1 - 20MHz). 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-302.Atmel ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.4 85°C 1.2 25°C -40°C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 506
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-303.Atmel ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.42 85°C 25°C -40°C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-304.Atmel ATmega1284: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 85°C 25°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 507
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-13. Additional current consumption for the different I/O modules (absolute values).
PAGE 508
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.4 Power-down supply current Figure 29-305.Atmel ATmega1284: Power-down supply current vs. VCC (watchdog timer disabled). 4.0 85°C 3.5 3.0 ICC [µA] 2.5 2.0 1.5 1.0 0.5 0 1.5 25°C -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-306.Atmel ATmega1284: Power-down supply current vs. VCC (watchdog timer enabled). 11.0 85°C 10.2 9.4 ICC [µA] 8.6 -40°C 25°C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 509
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.5 Power-save supply current Figure 29-307.Atmel ATmega1284: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 5.0 85°C 4.5 4.0 ICC [µA] 3.5 3.0 2.5 2.0 1.5 25°C -40°C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.7.6 Standby supply current Figure 29-308.Atmel ATmega1284: Standby supply current vs. VCC (watchdog timer disabled). 0.25 6MHz_xtal ICC [mA] 0.
PAGE 510
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.7 Pin pull-up Figure 29-309.Atmel ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 29-310.Atmel ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
PAGE 511
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-311.Atmel ATmega1284: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 29-312.Atmel ATmega1284: Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
PAGE 512
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-313.Atmel ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-314.Atmel ATmega1284: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
PAGE 513
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.8 Pin driver strength Figure 29-315.Atmel ATmega1284: I/O pin output voltage vs. sink current (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-316.Atmel ATmega1284: I/O pin output voltage vs. sink current (VCC = 3V). 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.
PAGE 514
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-317.Atmel ATmega1284: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-318.Atmel ATmega1284: I/O pin output voltage vs. source current (VCC = 2.7V). 3.0 VOH [V] 2.5 2.0 -40°C 25°C 1.5 85°C 1.0 0.
PAGE 515
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-319.Atmel ATmega1284: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 29.7.9 Pin threshold and hysteresis Figure 29-320.Atmel ATmega1284: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 516
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-321.Atmel ATmega1284: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C -40°C 25°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-322.Atmel ATmega1284: I/O pin input hysteresis vs. VCC. 0.60 Input hysteresis [mV] 0.55 85°C 25°C -40°C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 517
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-323.Atmel ATmega1284: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-324.Atmel ATmega1284: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 -40°C 85°C 25°C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 518
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-325.Atmel ATmega1284: Reset pin input hysteresis vs. VCC. 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.7.10 BOD threshold Figure 29-326.Atmel ATmega1284: BOD threshold vs. temperature (VBOT = 4.3V). 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
PAGE 519
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-327.Atmel ATmega1284: BOD threshold vs. temperature (VBOT = 2.7V). 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-328.Atmel ATmega1284: BOD threshold vs. temperature (VBOT = 1.8V). 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.
PAGE 520
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-329.Atmel ATmega1284: Calibrated bandgap voltage vs. VCC. 1.120 Bandgap voltage [V] 1.115 85°C 25°C 1.110 1.105 1.100 1.095 -40°C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 29-330.Atmel ATmega1284: Bandgap voltage vs. temperature. 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.
PAGE 521
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.7.11 Internal oscillator speed Figure 29-331.Atmel ATmega1284: Watchdog oscillator frequency vs. temperature. 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-332.Atmel ATmega1284: Watchdog oscillator frequency vs. VCC. 124 122 FRC [kHz] -40°C 120 25°C 118 116 85°C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 522
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-333.Atmel ATmega1284: Calibrated 8MHz RC oscillator vs. VCC. 8.6 85°C 8.4 25°C FRC [MHz] 8.2 8.0 -40°C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-334.Atmel ATmega1284: Calibrated 8MHz RC oscillator vs. temperature. 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.
PAGE 523
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-335.Atmel ATmega1284: Calibrated 8MHz RC oscillator vs. OSCCAL value. 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 29.7.12 Current consumption of peripheral units Figure 29-336.Atmel ATmega1284: ADC current vs. VCC (AREF = AVCC). 280 -40°C 25°C 85°C 260 240 ICC [µA] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 524
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-337.Atmel ATmega1284: Analog comparator current vs. VCC. 85 -40°C 25°C 85°C 75 ICC [µA] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-338.Atmel ATmega1284: AREF external reference current vs. VCC. 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 525
ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [µA] Figure 29-339.Atmel ATmega1284: Brownout detector current vs. VCC. 25 85°C 23 25°C 21 -40°C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-340.Atmel ATmega1284: Programming current vs. VCC. 14 -40°C 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 526
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-341.Atmel ATmega1284: Watchdog timer current vs. VCC. 8.5 -40°C 7.5 25°C 85°C ICC [µA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.7.13 Current consumption in reset and reset pulsewidth Figure 29-342.Atmel ATmega1284: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
PAGE 527
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-343.Atmel ATmega1284: Reset supply current vs. frequency (1 - 20MHz). 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-344.Atmel ATmega1284: Minimum reset pulsewidth vs. VCC. 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 528
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8 29.8.1 ATmega1284P typical characteristics Active supply current ICC [mA] Figure 29-345.Atmel ATmega1284P: Active supply current vs. low frequency (0.1 - 1.0MHz). 1.6 5.5V 1.4 5.0V 1.2 4.5V 1.0 4.0V 0.8 3.3V 0.6 2.7V 0.4 1.8V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency [MHz] Figure 29-346.Atmel ATmega1284P: Active supply current vs. frequency (1 - 20MHz). 20 5.5V 18 5.0V 16 4.5V ICC [mA] 14 12 4.0V 10 8 3.
PAGE 529
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-347.Atmel ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 8MHz). 9 85°C 25°C -40°C 8 7 ICC [mA] 6 5 4 3 2 1 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-348.Atmel ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 1MHz). 1.8 85°C 25°C -40°C 1.5 ICC [mA] 1.2 0.9 0.6 0.3 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 530
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-349.Atmel ATmega1284P: Active supply current vs. VCC (internal RC oscillator, 128kHz). 0.28 -40°C 25°C 85°C 0.24 ICC [mA] 0.20 0.16 0.12 0.08 0.04 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.8.2 Idle supply current Figure 29-350.Atmel ATmega1284P: Idle supply current vs. low frequency (0.1 - 1.0MHz). 0.24 5.5V 0.21 5.0V 0.18 4.5V 4.0V 3.6V ICC [mA] 0.15 0.12 2.7V 0.09 1.8V 0.06 0.03 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
PAGE 531
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-351.Atmel ATmega1284P: Idle supply current vs. frequency (1 - 20MHz). 3.0 5.5V 2.5 5.0V 4.5V ICC [mA] 2.0 1.5 4.0V 1.0 3.3V 2.7V 0.5 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-352.Atmel ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 8MHz). 1.4 85°C 1.2 25°C -40°C ICC [mA] 1.0 0.8 0.6 0.4 0.2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 532
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-353.Atmel ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 1MHz). 0.42 85°C 25°C -40°C 0.36 ICC [mA] 0.30 0.24 0.18 0.12 0.06 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-354.Atmel ATmega1284P: Idle supply current vs. VCC (internal RC oscillator, 128kHz). 0.12 -40°C 85°C 25°C 0.10 ICC [mA] 0.08 0.06 0.04 0.02 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 533
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.3 Supply current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See ”PRR0 – Power Reduction Register 0” on page 48 for details. Table 29-15. Additional current consumption for the different I/O modules (absolute values).
PAGE 534
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.4 Power-down supply current Figure 29-355.Atmel ATmega1284P: Power-down supply current vs. VCC (watchdog timer disabled). 4.0 85°C 3.5 3.0 ICC [µA] 2.5 2.0 1.5 1.0 0.5 0 1.5 25°C -40°C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-356.Atmel ATmega1284P: Power-down supply current vs. VCC (watchdog timer enabled). 11.0 85°C 10.2 9.4 ICC [µA] 8.6 -40°C 25°C 7.8 7.0 6.2 5.4 4.6 3.8 3.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 535
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.5 Power-save supply current Figure 29-357.Atmel ATmega1284P: Power-save supply current vs. VCC (watchdog timer disabled and 32kHz crystal oscillator running). 5.0 85°C 4.5 4.0 ICC [µA] 3.5 3.0 2.5 2.0 1.5 25°C -40°C 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.8.6 Standby supply current Figure 29-358.Atmel ATmega1284P: Standby supply current vs. VCC (watchdog timer disabled). 0.25 6MHz_xtal ICC [mA] 0.
PAGE 536
ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.7 Pin pull-up Figure 29-359.Atmel ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 29-360.Atmel ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 2.7V). 80 70 60 IOP [µA] 50 40 30 20 -40°C 25°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-361.Atmel ATmega1284P: I/O pin pull-up resistor current vs. input voltage (VCC = 5V). 140 120 IOP [µA] 100 80 60 40 -40°C 25°C 85°C 20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOP [V] Figure 29-362.Atmel ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 1.8V). 35 30 IRESET [µA] 25 20 15 10 -40°C 25°C 85°C 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.
PAGE 538
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-363.Atmel ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 2.7V). 60 50 IRESET [µA] 40 30 20 25°C -40°C 85°C 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VRESET [V] Figure 29-364.Atmel ATmega1284P: Reset pull-up resistor current vs. reset pin voltage (VCC = 5V). 120 100 IRESET [µA] 80 60 40 20 -40°C 25°C 85°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.8 Pin driver strength Figure 29-365.Atmel ATmega1284P: I/O pin output voltage vs. sink current (VCC = 2.7V). 1.2 85°C VOL [V] 1.0 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-366.Atmel ATmega1284P: I/O pin output voltage vs. sink current (VCC = 3V). 0.9 85°C 0.8 0.7 25°C VOL [V] 0.6 -40°C 0.5 0.4 0.3 0.2 0.
PAGE 540
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-367.Atmel ATmega1284P: I/O pin output voltage vs. sink current (VCC = 5V). 0.6 85°C 0.5 25°C VOL [V] 0.4 -40°C 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 IOL [mA] Figure 29-368.Atmel ATmega1284P: I/O pin output voltage vs. source current (VCC = 2.7V). 3.0 VOH [V] 2.5 2.0 -40°C 25°C 1.5 85°C 1.0 0.
PAGE 541
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-369.Atmel ATmega1284P: I/O pin output voltage vs. source current (VCC = 3V). 3.5 3.0 VOH [V] 2.5 -40°C 25°C 85°C 2.0 1.5 1.0 0.5 0 0 2 4 6 8 10 12 14 16 18 20 IOH [mA] 29.8.9 Pin threshold and hysteresis Figure 29-370.Atmel ATmega1284P: I/O pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). 3.0 85°C 25°C -40°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 542
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-371.Atmel ATmega1284P: I/O pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 85°C -40°C 25°C Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-372.Atmel ATmega1284P: I/O pin input hysteresis vs. VCC. 0.60 Input hysteresis [mV] 0.55 85°C 25°C -40°C 0.50 0.45 0.40 0.35 0.30 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 543
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-373.Atmel ATmega1284P: Reset pin input threshold vs. VCC (VIH , I/O pin read as ‘1’). -40°C 85°C 25°C 2.5 Threshold [V] 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-374.Atmel ATmega1284P: Reset pin input threshold vs. VCC (VIL, I/O pin read as ‘0’). 2.5 -40°C 85°C 25°C Threshold (V) 2.0 1.5 1.0 0.5 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PAGE 544
ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-375.Atmel ATmega1284P: Reset pin input hysteresis vs. VCC. 0.6 Input hysteresis [mV] 0.5 0.4 0.3 0.2 0.1 -40°C 25°C 85°C 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.8.10 BOD threshold Figure 29-376.Atmel ATmega1284P: BOD threshold vs. temperature (VBOT = 4.3V). 4.37 Rising Vcc 4.35 Threshold [V] 4.33 4.31 Falling Vcc 4.29 4.27 4.25 4.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-377.Atmel ATmega1284P: BOD threshold vs. temperature (VBOT = 2.7V). 2.78 Rising Vcc 2.76 Threshold [V] 2.74 2.72 2.70 Falling Vcc 2.68 2.66 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-378.Atmel ATmega1284P: BOD threshold vs. temperature (VBOT = 1.8V). 1.84 Rising Vcc 1.83 Threshold [V] 1.82 1.81 Falling Vcc 1.80 1.79 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-379.Atmel ATmega1284P: Calibrated bandgap voltage vs. VCC. 1.120 Bandgap voltage [V] 1.115 85°C 25°C 1.110 1.105 1.100 1.095 -40°C 1.090 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Vcc [V] Figure 29-380.Atmel ATmega1284P: Bandgap voltage vs. temperature. 1.120 1.8V 3.3V 5.0V 5.5V Bandgap voltage [V] 1.115 1.110 1.105 1.100 1.095 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 29.8.11 Internal oscillator speed Figure 29-381.Atmel ATmega1284P: Watchdog oscillator frequency vs. temperature. 123 122 121 FRC [kHz] 120 119 118 117 2.7V 116 3.3V 4.0V 5.5V 115 114 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature [°C] Figure 29-382.Atmel ATmega1284P: Watchdog oscillator frequency vs. VCC. 124 122 FRC [kHz] -40°C 120 25°C 118 116 85°C 114 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-383.Atmel ATmega1284P: Calibrated 8MHz RC oscillator vs. VCC. 8.6 85°C 8.4 25°C FRC [MHz] 8.2 8.0 -40°C 7.8 7.6 7.4 7.2 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-384.Atmel ATmega1284P: Calibrated 8MHz RC oscillator vs. temperature. 8.3 5.5V 8.2 3.3V 2.7V FRC [MHz] 8.1 1.8V 8.0 7.9 7.8 7.7 7.6 7.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-385.Atmel ATmega1284P: Calibrated 8MHz RC oscillator vs. OSCCAL value. 16 85°C 25°C -40°C 14 FRC [MHz] 12 10 8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL [X1] 29.8.12 Current consumption of peripheral units Figure 29-386.Atmel ATmega1284P: ADC current vs. VCC (AREF = AVCC). 280 -40°C 25°C 85°C 260 240 ICC [µA] 220 200 180 160 140 120 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-387.Atmel ATmega1284P: Analog comparator current vs. VCC. 85 -40°C 25°C 85°C 75 ICC [µA] 65 55 45 35 25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-388.Atmel ATmega1284P: AREF external reference current vs. VCC. 200 85°C 25°C -40°C 180 ICC [µA] 160 140 120 100 80 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P ICC [µA] Figure 29-389.Atmel ATmega1284P: Brownout detector current vs. VCC. 25 85°C 23 25°C 21 -40°C 19 17 15 13 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] Figure 29-390.Atmel ATmega1284P: Programming current vs. VCC. 14 -40°C 12 ICC [mA] 10 25°C 8 85°C 6 4 2 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-391.Atmel ATmega1284P: Watchdog timer current vs. VCC. 8.5 -40°C 7.5 25°C 85°C ICC [µA] 6.5 5.5 4.5 3.5 2.5 1.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC [V] 29.8.13 Current consumption in reset and reset pulsewidth Figure 29-392.Atmel ATmega1284P: Reset supply current vs. low frequency (0.1 - 1.0MHz). 0.10 5.5V 5.0V 0.08 ICC [mA] 4.5V 4.0V 0.06 3.3V 0.04 2.7V 1.8V 0.02 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Figure 29-393.Atmel ATmega1284P: Reset supply current vs. frequency (1 - 20MHz). 1.6 5.5V 1.4 5.0V 1.2 4.5V ICC [mA] 1.0 0.8 4.0V 0.6 3.3V 0.4 2.7V 0.2 1.8V 0 0 2 4 6 8 10 12 14 16 18 20 Frequency [MHz] Figure 29-394.Atmel ATmega1284P: Minimum reset pulsewidth vs. VCC. 1800 1600 Pulsewidth [ns] 1400 1200 1000 800 600 400 85°C 25°C -40°C 200 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 30.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Address (0xC0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page UCSR0A Name RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 193/208 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 - 239 (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 236 (0xBB) TWDR (0xBA) TWAR TWA6 TWA5 TWA4 TWA3 two-wire Serial Interface Data Register TWA2 TWA1
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ATmega164A/PA/324A/PA/644A/PA/1284/P Address Name (0x7E) DIDR0 (0x7D) Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 263 - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 259 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 242 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 261 (0x79) ADCH ADC Data Register High byte (0x78) ADCL ADC Data Register L
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ATmega164A/PA/324A/PA/644A/PA/1284/P Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1C (0x3C) Address EIFR Name - - - - - INTF2 INTF1 INTF0 68 0x1B (0x3B) PCIFR - - - - PCIF3 PCIF2 PCIF1 PCIF0 69 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) TIFR3 - - ICF3 - - OCF3B OCF3A TOV3 141 0x17 (0x37) TIFR2 - - - - - OCF2B OCF2A TOV2 163 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1
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ATmega164A/PA/324A/PA/644A/PA/1284/P 31.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd L
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ATmega164A/PA/324A/PA/644A/PA/1284/P Mnemonics Operands Description Operation Flags #Clocks PUSH Rr Push Register on Stack STACK  Rr None 2 POP Rd Pop Register from Stack Rd  STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32. Ordering information 32.1 Atmel ATmega164A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega164A-AU ATmega164A-AUR(5) ATmega164A-PU ATmega164A-MU ATmega164A-MUR(5) ATmega164A-MCH(4) ATmega164A-MCHR(4)(5) ATmega164A-CU ATmega164A-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.2 Atmel ATmega164PA Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega164PA-AU ATmega164PA-AUR(5) ATmega164PA-PU ATmega164PA-MU ATmega164PA-MUR(5) ATmega164PA-MCH(4) ATmega164PA-MCHR(4)(5) ATmega164PA-CU ATmega164PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.3 Atmel ATmega324A Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega324A-AU ATmega324A-AUR(5) ATmega324A-PU ATmega324A-MU ATmega324A-MUR(5) ATmega324A-MCH(4) ATmega324A-MCHR(4)(5) ATmega324A-CU ATmega324A-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.4 Atmel ATmega324PA Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega324PA-AU ATmega324PA-AUR(5) ATmega324PA-PU ATmega324PA-MU ATmega324PA-MUR(5) ATmega324PA-MCH(4) ATmega324PA-MCHR(4)(5) ATmega324PA-CU ATmega324PA-CUR(5) 44A 44A 40P6 44M1 44M1 44MC 44MC 49C2 49C2 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.5 Atmel ATmega644A Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) Package(1) ATmega644A-AU ATmega644A-AUR(4) ATmega644A-PU ATmega644A-MU ATmega644A-MUR(4) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.6 Atmel ATmega644PA Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega644PA-AU ATmega644PA-AUR(4) ATmega644PA-PU ATmega644PA-MU ATmega644PA-MUR(4) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.7 Atmel ATmega1284 Speed [MHz](3) 20 Notes: Power supply 1.8 - 5.5V Ordering code(2) Package(1) ATmega1284-AU ATmega1284-AUR(4) ATmega1284-PU ATmega1284-MU ATmega1284-MUR(4) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 32.8 Atmel ATmega1284P Speed [MHz] (3) 20 Notes: Power supply 1.8 - 5.5V Ordering code (2) Package (1) ATmega1284P-AU ATmega1284P-AUR(4) ATmega1284P-PU ATmega1284P-MU ATmega1284P-MUR(4) 44A 44A 40P6 44M1 44M1 Operational range Industrial (-40oC to 85oC) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 33. Packaging information 33.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 33.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 33.3 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 33.4 44MC C Pin 1 ID D SIDE VIEW y A1 E A TOP VIEW eT/2 A19 eR A24 B20 B16 A1 A18 COMMON DIMENSIONS (Unit of Measure = mm) B1 B15 b R0.20 0.40 D2 eT SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.23 0.30 C B5 B11 A6 A13 B10 B6 A12 L 0.20 REF D 4.90 5.00 5.10 D2 2.55 2.60 2.65 E 4.90 5.00 5.10 E2 2.55 2.60 2.65 eT – 0.70 – eR – 0.40 – K 0.45 – – L 0.30 0.35 0.40 y 0.00 – 0.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 33.5 49C2 E A1 BALL ID 0.10 D A1 TOP VIEW A A2 SIDE VIEW E1 G e F E D D1 COMMON DIMENSIONS (Unit of Measure = mm) C B 1 A1 BALL CORNER MIN NOM MAX A – – 1.00 A1 0.20 – – A2 0.65 – – D 4.90 5.00 5.10 SYMBOL A 2 3 4 5 b 6 7 e BOTTOM VIEW 49 - Ø0.35 ±0.05 D1 E 3.90 BSC 4.90 5.00 E1 b NOTE 5.10 3.90 BSC 0.30 0.35 e 0.40 0.65 BSC 3/14/08 Package Drawing Contact: packagedrawings@atmel.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 34. Errata 34.1 34.1.1 Errata for ATmega164A Rev. E No known Errata. 34.2 34.2.1 Errata for ATmega164PA Rev. E No known Errata. 34.3 34.3.1 Errata for ATmega324A Rev. F No known Errata. 34.4 34.4.1 Errata for ATmega324PA Rev. F No known Errata. 34.5 34.5.1 Errata for ATmega644A Rev. F No known Errata. 34.6 34.6.1 Errata for ATmega644PA Rev. F No known Errata. 34.7 34.7.1 Errata for ATmega1284 Rev. B No known Errata. 34.8 34.8.1 Errata for ATmega1284P Rev.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 35. Datasheet revision history Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 Rev. 8272E - 04/2013 1. Updated Figure 1-1 on page 2 and Figure 2-1 on page 5: T3 and T/C3 only available in ATmega1284/1284P. 2. Updated descriptive text on page 6 to indicate that ATmega1284/1284P has four T/Cs. 3. 4. 5. 6. 7.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 35.4 Rev. 8272B - 05/11 1. 2. 3. 4. 5. 6. 35.5 Added Atmel QTouch Library Support and QTouch Sensing Capability Features. Replaced the Figure 1-1 on page 2 by an updated “Pinout.” that includes Timer/Counter3. Replaced the Figure 7-1 on page 10 by an updated “Block diagram of the AVR architecture.” that includes Timer/Counter3. Added ”RAMPZ – Extended Z-pointer Register for ELPM/SPM(1)” on page 15. Added ”PRR1 – Power Reduction Register 1” on page 49.
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ATmega164A/PA/324A/PA/644A/PA/1284/P – Updated ”Signature Bytes” on page 301 and ”Page Size” on page 301 – Added ”DC Characteristics” on page 330 for non-picoPower devices.
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ATmega164A/PA/324A/PA/644A/PA/1284/P Table of Contents Features ..................................................................................................... 1 1 Pin configurations ................................................................................... 2 1.1Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P 2 1.2Pinout - DRQFN for Atmel ATmega164A/164PA/324A/324PA .................................3 1.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 9.2Clock Sources .........................................................................................................31 9.3Low Power Crystal Oscillator ...................................................................................33 9.4Full swing Crystal Oscillator ....................................................................................34 9.5Low Frequency Crystal Oscillator ............................................................................
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ATmega164A/PA/324A/PA/644A/PA/1284/P 13.1Overview ...............................................................................................................67 13.2Register description ...............................................................................................67 14 I/O-Ports .................................................................................................. 72 14.1Overview ................................................................................................
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ATmega164A/PA/324A/PA/644A/PA/1284/P 17.5Output Compare unit ...........................................................................................145 17.6Compare Match Output unit ................................................................................147 17.7Modes of operation ..............................................................................................148 17.8Timer/Counter Timing diagrams ..........................................................................152 17.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 21 Two-wire Serial Interface ..................................................................... 211 21.1Features ..............................................................................................................211 21.2Two-wire Serial Interface bus definition ...............................................................211 21.3Data Transfer and Frame Format ........................................................................212 21.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 270 25.1Features ..............................................................................................................270 25.2Overview .............................................................................................................270 25.3Data Registers .....................................................................................................271 25.
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ATmega164A/PA/324A/PA/644A/PA/1284/P 28.4System and reset characteristics ........................................................................338 28.5External interrupts characteristics .......................................................................338 28.6SPI timing characteristics ....................................................................................339 28.7two-wire Serial Interface Characteristics .............................................................340 28.
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34.3Errata for ATmega324A ......................................................................................574 34.4Errata for ATmega324PA ....................................................................................574 34.5Errata for ATmega644A ......................................................................................574 34.6Errata for ATmega644PA ....................................................................................574 34.7Errata for ATmega1284 ........................
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 16F, Shin Osaki Kangyo Bldg.