Datasheet

89
7674F–AVR–09/09
ATmega164P/324P/644P
Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
(1)
Signal Name
PD3/INT1/TXD1/
PCINT27
PD2/INT0/RXD1/
PCINT26
PD1/TXD0/
PCINT25
PD0/RXD0/
PCINT27
PUOE 0 TXEN RXEN
PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTD0 • PUD
DDOE 0 RXEN1 TXEN RXEN
DDOV 0 0 SDA_OUT SCL_OUT
PVOE 0 0 TWEN TWEN
PVOV0000
DIEOE
INT1 ENABLE
PCINT27 • PCIE3
INT2 ENABLE
PCINT26 • PCIE3
INT1 ENABLE
PCINT25 • PCIE3
INT0 ENABLE
PCINT24 • PCIE3
DIEOV1111
DI
INT1 INPUT
PCINT27 INPUT
INT0 INPUT
PCINT27 INPUT
TXD
PCINT25 INPUT
RXD
PCINT24 INPUT
AIO––––